Two layer quad bit error correction

Patent metadata

Field	Value
Publication number	US-10102064-B1
Application number	US-201514923565-A
Country	US
Kind code	B1
Filing date	Oct 27, 2015
Priority date	Oct 27, 2015
Publication date	Oct 16, 2018
Grant date	Oct 16, 2018

Abstract

A memory device includes one or more memory arrays and a quad bit error correction circuit. The quad bit error correction circuit may include a first layer error correction circuit and a second layer error correction circuit. The first layer error correction circuit may be configured to generate a Hamming correction bit vector, and the second layer error correction circuit may be configured to generate a Golay correction bit vector. The Hamming correction bit vector and the Golay correction bit vector may be used to identify up to four correctable bit errors in data to be stored in the one more memory arrays.

First claim

What is claimed is:

1. A memory device, comprising:
one or more memory arrays;
an error correction circuit configured to process data to be stored in the one or more memory arrays, the error correction circuit comprising:
a first layer error correction circuit, wherein the first layer error correction circuit comprises a plurality of Hamming coders, wherein each Hamming coder of the plurality of Hamming coders is configured to:
receive the data to be stored in the one or more memory arrays,
process the data to generate a first Hamming code and a second Hamming code, and
generate a Hamming correction bit vector based on the first Hamming code and the second Hamming code; and

a second layer error correction circuit, wherein the second layer error correction circuit comprises a plurality of sets of Golay coders, wherein each set of the plurality of sets of Golay coders is configured to:
receive the data to be stored in the one or more memory arrays,
process the data to generate a first Golay code and a second Golay code, and
generate a Golay correction bit vector based on the first Golay code and the second Golay code;

wherein each of the Hamming correction bit vector and the Golay correction bit vector is a representation of one or more error(s) within the data, wherein one of the first layer error correction circuit or the second layer error correction circuit is configured to correct errors within the data missed by the other of the first layer error correction circuit or the second layer error correction circuit, and wherein the error correction circuit is configured to correct quad bit errors.

2. The memory device as recited in claim 1 , wherein each Hamming coder of the plurality of Hamming coders is associated with two sets of Golay coders.

3. The memory device as recited in claim 1 , wherein at least one set of Golay coders comprises a first Golay (22, 11) coder, a second Golay (22, 11) coder, and a Golay (21, 10) coder.

4. The memory device as recited in claim 1 , wherein at least one of the plurality of Hamming coders is a Hamming (72, 64) coder.

5. The memory device as recited in claim 1 , wherein no more than three Golay code bits generated by a Golay coder of one of the plurality of sets of Golay coders are stored in a byte of the one or more memory arrays.

6. The memory device as recited in claim 1 , wherein no more than three Golay code bits generated by a Golay coder of the plurality of sets of Golay coders are stored in a bit column of the one or more memory arrays.

7. A method comprising:
receiving, by a memory device, data bits to be stored in one or more memory arrays;
processing, by one or more Hamming coders, the data bits to generate a Hamming correction bit vector, wherein the Hamming correction bit vector is a first representation of errors within the data bits;
processing, by one or more Golay coders, the data bits to generate a Golay correction bit vector, wherein the Golay correction bit vector is a second representation of errors within the data bits; and
correcting, by an error correction circuit, quad bit errors within the data bits based on the first representation of errors and the second representation of errors within the data bits, wherein one of the Hamming correction bit vector or the Golay correction bit vector represents bit errors missed by the other of the Hamming correction bit vector or the Golay correction bit vector.

8. The method as recited in claim 7 , wherein:
the one or more Hamming coders comprises eight Hamming (72, 64) coders;
the one or more Golay coders are arranged in sixteen sets of Golay coders, wherein individual sets of Golay coders comprises a first Golay (22, 11) coder, a second Golay (22, 11) coder, and a Golay (21, 10) coder; and
each of the eight Hamming (72, 64) coders is associated with two of the sixteen sets of Golay coders.

9. The method as recited in claim 8 , wherein a number of the data bits processed by individual ones of the sixteen sets of Golay coders is half the number of the data bits processed by individual ones of the eight Hamming (72, 64) coders.

10. The method as recited in claim 7 , wherein no more than three Golay code bits generated by a Golay coder of the one or more Golay coders is stored in a byte of the one or more memory arrays.

11. The method as recited in claim 7 , wherein no more than three Golay code bits generated by a Golay coder of the one or more Golay coders is stored in a bit column of the one or more memory arrays.

12. The method as recited in claim 7 , wherein the data bits are processed by the one or more Hamming coders in blocks of 64 bits.

Assignees

• Everspin Technologies Inc

Inventors

• Baty Kurt

Classifications

• G06F11/1012

  using codes or arrangements adapted for a specific type of error (G06F11/1048 takes precedence) · CPC title

• H03M13/1505

  Golay Codes · CPC title

• H03M13/19

  Single error correction without using particular properties of the cyclic codes, e.g. Hamming codes, extended or generalised Hamming codes · CPC title

• G06F11/1076 Primary

  Parity data used in redundant arrays of independent storages, e.g. in RAID systems · CPC title

• H03M13/13

  Linear codes · CPC title