Multicore, multibank, fully concurrent coherence controller

Patent metadata

Field	Value
Publication number	US-9652404-B2
Application number	US-201615047318-A
Country	US
Kind code	B2
Filing date	Feb 18, 2016
Priority date	Oct 24, 2012
Publication date	May 16, 2017
Grant date	May 16, 2017

Abstract

This invention optimizes non-shared accesses and avoids dependencies across coherent endpoints to ensure bandwidth across the system even when sharing. The coherence controller is distributed across all coherent endpoints. The coherence controller for each memory endpoint keeps a state around for each coherent access to ensure the proper ordering of events. The coherence controller of this invention uses First-In-First-Out allocation to ensure full utilization of the resources before stalling and simplicity of implementation. The coherence controller provides Snoop Command/Response ID Allocation per memory endpoint.

First claim

What is claimed is:

1. A method of coherent data processing system comprising the steps of:
temporarily storing data in a cache memory of at least one processing core of a plurality of processing cores;
storing data in a plurality of memory endpoints;
storing each of a plurality of coherence maintenance addresses in a corresponding entry, each entry storing an address of an access request committed to a shared memory at a corresponding memory endpoint and an assigned ID tag;
assigning an available ID tag from a set of ID tags to the entry of an access request committed to the shared memory for storage;
retiring a coherence maintenance address entry upon receipt of a completion signal from the shared memory indicating completion of the corresponding access request; and
comparing the address of a memory access request with all stored coherence maintenance addresses; and
generating a hazard stall signal if the address of a memory access request matches any stored coherence maintenance address.

2. The method of data processing system of claim 1 , wherein:
storing dirty tags corresponding to coherence write data and an assigned ID tag in a coherence maintenance address entry corresponding to each write access request;
receiving dirty tags corresponding to snoop response data;
determining where snoop response dirty tags indicate dirty and said stored dirty tags indicate clean;
writing snoop response data that is dirty in the snoop response and clean in the coherence write data to the corresponding memory endpoint; and
assigning an available ID tag from said set of ID tags upon creation of an coherence transaction tracking entry corresponding to each write access request.

3. The method processing system of claim 1 , wherein:
said step of assigning an available ID tag assigns a lowest available ID tag upon allocating an ID tag.

4. The method data processing system of claim 1 , wherein:
said step of storing data in a plurality of memory endpoints includes a plurality of independently accessible memory banks.

5. The method data processing system of claim 4 , wherein:
each of said plurality of independently accessible memory banks includes a plurality of virtual subbanks.

Assignees

• Texas Instruments Inc

Inventors

• Pierson Matthew D
• Chirca Kai

Classifications

• G06F12/0831 Primary

  using a bus scheme, e.g. with bus monitoring or watching means · CPC title

• Y02B60/1225

  Cross-Sectional Technologies · mapped topic

• G06F2212/62

  Details of cache specific to multiprocessor cache arrangements · CPC title

• G06F13/42

  Bus transfer protocol, e.g. handshake; Synchronisation · CPC title

• Y02B60/1235

  Cross-Sectional Technologies · mapped topic