Distributed error detection and correction with hamming code handoff

Patent metadata

Field	Value
Publication number	US-11347644-B2
Application number	US-201916653324-A
Country	US
Kind code	B2
Filing date	Oct 15, 2019
Priority date	Oct 15, 2018
Publication date	May 31, 2022
Grant date	May 31, 2022

Abstract

A device includes a data path, a first interface connected to the data path and configured to receive a request from a processor package to write a data value to a memory address, and a controller connected to the data path and configured to receive the request to write the data value to the memory address and to calculate a Hamming code of the data value. The controller is configured to transmit the data value and the Hamming code on the data path. The device includes an external memory interleave connected to the data path. The external memory interleave is configured to receive the data value and calculate a test Hamming code of the data value and to determine whether to send the data value to an external memory interface to be written to the memory address based on a comparison of the Hamming code and the test Hamming code.

First claim

What is claimed is:

1. A device comprising:
a data path;
a first interface connected to the data path and configured to receive a request from a processor package to write a data value to a memory address;
a controller connected to the data path and configured to:
receive the request to write the data value to the memory address;
calculate a Hamming code of the data value; and
transmit the data value and the Hamming code on the data path;

a queue connected to the data path and configured to:
receive the data value and the Hamming code on the data path from the controller;
calculate a first test Hamming code of the data value;
determine a first number of bit errors associated with the data value based on a comparison of the Hamming code and the first test Hamming code;
in response to the first number of bit errors being greater than one, transmit an error code;
in response to the first number of bit errors being equal to one, correct the data value to generate queue output data on the data path; and
in response to first the number of bit errors being zero, output the data value on the data path as queue output data;

an external memory interface; and
an external memory interleave connected to the data path and to the external memory interface, the external memory interleave configured to:
separate address spaces assigned to the external memory interface;
receive the queue output data and the Hamming code;
calculate a second test Hamming code of the queue output data;
determine a second number of bit errors associated with the queue output data based on a comparison of the Hamming code and the second test Hamming code;
in response to the second number of bit errors being greater than one, transmit an error code;
in response to the second number of bit errors being equal to one, correct the queue output data to generate output data values and transmit the corrected data values and the Hamming code to an external memory device; and
in response to the second number of bit errors being equal to zero, transmit the queue output data as the output data values and the Hamming code to the external memory device.

2. The device of claim 1 , wherein the Hamming code includes an out of band Hamming code located either before or after the data value.

3. The device of claim 1 , wherein the controller is further configured to determine Hamming code of the memory address and to transmit the memory address and the Hamming code of the memory address on the data path with the data value and the Hamming code of the data value.

4. The device of claim 1 , further comprising a snoop filter bank configured to store a snoop filter state indicating a status of the memory address with a cache of the processor package, wherein the controller is configured to:
calculate a parity bit based on the snoop filter state; and
store the snoop filter state and the parity bit in the snoop filter bank.

5. The device of claim 1 , wherein the controller is further configured to:
issue a request to read a second memory address to the external memory interleave;
determine an address Hamming code of the second memory address;
receive a result of the request to read the second memory address from the external memory interleave, the result including a stored Hamming code; and
perform an exclusive OR operation on the address Hamming code and the stored Hamming code to remove the stored Hamming code from the result.

6. A system comprising:
a processor package;
an external memory device; and
a multi-core shared memory controller (MSMC) including:
a data path;
a first interface connected to the data path and the processor package, wherein the first interface is configured to receive a request from the processor package to write a data value to a memory address of the external memory device;
a controller connected to the data path and configured to:
receive the request to write the data value to the memory address;
calculate a Hamming code of the data value; and
transmit the data value and the Hamming code on the data path;

a queue connected to the data path and configured to:
receive the data value on the data path from the controller;
calculate a first test Hamming code of the data value;
determine a first number of bit errors associated with the data value based on a comparison of the Hamming code and the first test Hamming code;
in response to the first number of bit errors being greater than one, transmit an error code;
in response to the first number of bit errors being equal to one, correct the data value to generate queue output data on the data path; and
in response to first the number of bit errors being zero, output the data value on the data path as queue output data;

an external memory interface connected to the external memory device;
an external memory interleave connected to the data path and to the external memory interface, the external memory interleave configured to:
separate address spaces assigned to the external memory interface;
receive the queue output data and the Hamming code;
calculate a second test Hamming code of the queue output data;
determine a second number of bit errors associated with the queue output data based on a comparison of the Hamming code and the second test Hamming code;
in response to the second number of bit errors being greater than one, transmit an error code;
in response to the second number of bit errors being equal to one, correct the queue output data to generate output data values and transmit the corrected data values and the Hamming code to the external memory device; and
in response to the second number of bit errors being equal to zero, transmit the queue output data as the output data values and the Hamming code to the external memory device.

7. The system of claim 6 , wherein the Hamming code includes an out of band Hamming code.

8. The system of claim 6 , wherein the controller is further configured to determine Hamming code of the memory address and to transmit the memory address and the Hamming code of the memory address on the data path with the data value and the Hamming code of the data value.

9. The system of claim 6 , further comprising a snoop filter bank configured to store a snoop filter state indicating a status of the memory address with a cache of the processor package, wherein the controller is configured to:
calculate a parity bit based on the snoop filter state; and
store the snoop filter state and the parity bit in the snoop filter bank.

10. The system of claim 6 , wherein the controller is further configured to:
issue a request to read a second memory address to the external memory interleave;
determine an address Hamming code of the second memory address;
receive a result of the request to read the second memory address from the external memory interleave, the result including a stored Hamming code; and
perform an exclusive OR operation on the address Hamming code and the stored Hamming code to remove the stored Hamming code from the result.

11. A method comprising:
receiving, at a controller of a multi-core shared memory controller (MSMC), a request to write a data value to a memory address of an external memory device connected to the MSMC;
calculating, a Hamming code of the data value;
transmitting the data value and the Hamming code to a queue connected to a data path,
wherein the queue is configured to:
receive the data value and the Hamming code on the data path from the controller;
calculate a first test Hamming code of the data value;
determine a first number of bit errors associated with the data value based on a comparison of the Hamming code and the first

Assignees

• Texas Instruments Inc

Inventors

• Chirca Kai
• Wu Daniel
• Pierson Matthew David

Classifications

• G06F12/084 Primary

  with a shared cache · CPC title

• G06F3/0604

  Improving or facilitating administration, e.g. storage management · CPC title

• G06F11/1004 Primary

  to protect a block of data words, e.g. CRC or checksum (G06F11/1076 takes precedence; security arrangements for protecting computers or computer systems against unauthorized activity G06F21/00) · CPC title

• G06F3/0679

  Non-volatile semiconductor memory device, e.g. flash memory, one time programmable memory [OTP] · CPC title

• G06F2212/1008

  Correctness of operation, e.g. memory ordering · CPC title