Deep trench isolation structures resistant to cracking

Patent metadata

Field	Value
Publication number	US-12453203-B2
Application number	US-202217658704-A
Country	US
Kind code	B2
Filing date	Apr 11, 2022
Priority date	Jun 29, 2018
Publication date	Oct 21, 2025
Grant date	Oct 21, 2025

Abstract

A method includes etching a semiconductor substrate to form a trench, filling a dielectric layer into the trench, with a void being formed in the trench and between opposite portions of the dielectric layer, etching the dielectric layer to reveal the void, forming a diffusion barrier layer on the dielectric layer, and forming a high-reflectivity metal layer on the diffusion barrier layer. The high-reflectivity metal layer has a portion extending into the trench. A remaining portion of the void is enclosed by the high-reflectivity metal layer.

First claim

What is claimed is:

1. A structure comprising:
a semiconductor substrate;
a Deep Trench Isolation (DTI) region extending from a top surface of the semiconductor substrate into the semiconductor substrate, wherein the DTI region comprises:
a dielectric layer comprising:
a first portion in the semiconductor substrate; and
a second portion higher than the semiconductor substrate, wherein the second portion of the dielectric layer overlaps the semiconductor substrate;

a diffusion barrier layer over the dielectric layer; and
a high-reflectivity metal layer between opposite portions of the dielectric layer, wherein the high-reflectivity metal layer encloses a void therein, and wherein the diffusion barrier layer is between the dielectric layer and the high-reflectivity metal layer;

pixel units with portions in the semiconductor substrate;
color filters overlapping the pixel units; and
micro lenses overlapping the color filters.

2. The structure of claim 1 further comprising:
a shallow trench isolation region extending from a bottom surface of the semiconductor substrate into the semiconductor substrate, wherein the DTI region overlaps the shallow trench isolation region.

3. The structure of claim 1 , wherein the dielectric layer comprises a portion having opposite surfaces, wherein the opposite surfaces contact the semiconductor substrate and the diffusion barrier layer.

4. The structure of claim 1 , wherein the diffusion barrier layer comprises aluminum oxide.

5. The structure of claim 1 , wherein the diffusion barrier layer comprises tantalum oxide.

6. The structure of claim 1 , wherein the high-reflectivity metal layer has a reflectivity higher than about 90 percent.

7. The structure of claim 1 , wherein all portions of the high-reflectivity metal layer in the DTI region have thicknesses greater than about 150Å.

8. The structure of claim 1 , wherein the dielectric layer is non-conformal, and the diffusion barrier layer is a conformal layer.

9. The structure of claim 1 , wherein the DTI forms a grid pattern.

10. The structure of claim 1 , wherein in a cross-sectional view of the structure, the second portion of the dielectric layer and the semiconductor substrate form zigzag interfaces.

11. The structure of claim 1 , wherein the top surface of the semiconductor substrate forms pyramids, and wherein a top end of the void is higher than bottom ends of the pyramids.

12. A structure comprising:
a semiconductor substrate comprising a top surface;
a dielectric layer comprising lower portions and an upper portion, wherein the upper portion is over the semiconductor substrate;
a Deep Trench Isolation (DTI) grid extending into the semiconductor substrate, wherein the DTI grid comprises:
a void grid, wherein a top end of the void is higher than the top surface of the semiconductor substrate;
a metallic material enclosing the void grid therein, wherein the metallic material has a grid pattern;
and wherein the lower portions of the dielectric layer are underlying the metallic material;

color filters over the upper portion of the dielectric layer, wherein the color filters are vertically aligned to grid openings of the DTI grid; and
micro lenses over the color filters, wherein the micro lenses are aligned to the color filters.

13. The structure of claim 12 wherein the top surface of the semiconductor substrate forms pyramid patterns, wherein the upper portion of the dielectric layer comprises a bottom surface physically contacting the top surface of the semiconductor substrate to form zigzag interfaces.

14. The structure of claim 13 , wherein the dielectric layer comprises a planar top surface opposite to the bottom surface, and wherein the zigzag interfaces extend to an edge of the DTI grid and are joined to the lower portions of the dielectric layer.

15. The structure of claim 12 , wherein the dielectric layer comprises:
a bottom portion in the DTI grid, wherein the bottom portion is overlapped by the void grid; and
a sidewall portion on a side of the void grid, wherein the sidewall portion is thicker than the upper portion.

16. The structure of claim 15 further comprising a high-k dielectric layer in the DTI grid and under the metallic material, wherein the high-k dielectric layer is a conformal layer, wherein the high-k dielectric layer is between, and is in contact with both of, the metallic material and the dielectric layer.

17. The structure of claim 12 , wherein the metallic material comprises an additional upper portion in the upper portion of the dielectric layer that is higher than the semiconductor substrate.

18. The structure of claim 17 , wherein the void comprises a part in the upper portion of the dielectric layer that is higher than the semiconductor substrate.

19. A structure comprising:
a semiconductor substrate;
a first dielectric layer comprising a first portion and a second portion, with the first portion being over the semiconductor substrate and forming an interface with the semiconductor substrate, wherein a lower part of the second portion is lower than the first portion;
a deep trench isolation region extending into the semiconductor substrate, wherein the deep trench isolation region comprises:
a void;
a metallic material enclosing the void therein, wherein the metallic material comprises a part in the semiconductor substrate;
a diffusion barrier underlying the metallic material;
and wherein the second portion of the first dielectric layer is underlying the diffusion barrier;

a second dielectric layer over and contacting the first portion of the first dielectric layer, wherein a bottom surface of the second dielectric layer contacts top surfaces of both of the deep trench isolation region and the first dielectric layer; and
color filters over the second dielectric layer.

20. The structure of claim 19 , wherein the void forms a void grid that comprises a first plurality of parallel voids and a second plurality of parallel voids joining the first plurality of parallel voids, and wherein the first plurality of parallel voids are perpendicular to the second plurality of parallel voids.

Assignees

• Taiwan Semiconductor Mfg Co Ltd
• Taiwan Semiconductor Mfg Co Ltd

Inventors

• Wu Ming-Chi
• Fang Chun-Chieh
• Su Bo-Chang
• Tu Chien Nan
• Yeh Yu-Lung
• Lin Kun-Yu
• Chen Shih-Shiung

Classifications

• H10P50/283

  by chemical means · CPC title

• H10P50/242

  of Group IV materials · CPC title

• H10P14/412

  Deposition of metallic or metal-silicide materials · CPC title

• H10W10/17

  formed using trench refilling with dielectric materials, e.g. shallow trench isolations · CPC title

• H10W10/014

  using trench refilling with dielectric materials, e.g. shallow trench isolations · CPC title