Deep trench spacing isolation for complementary metal-oxide-semiconductor (CMOS) image sensors

Patent metadata

Field	Value
Publication number	US-9559134-B2
Application number	US-201414564196-A
Country	US
Kind code	B2
Filing date	Dec 9, 2014
Priority date	Dec 9, 2014
Publication date	Jan 31, 2017
Grant date	Jan 31, 2017

Abstract

An image sensor employing deep trench spacing isolation is provided. A plurality of pixel sensors is arranged over or within a semiconductor substrate. A trench is arranged in the semiconductor substrate around and between adjacent ones of the plurality of pixel sensors, and the trench has a gap located between sidewalls of the trench. A cap is arranged over or within the trench at a position overlying the gap. The cap seals the gap within the trench. A method of manufacturing the image sensor is also provided.

First claim

What is claimed is:

1. An image sensor comprising:
a plurality of pixel sensors arranged over or within a semiconductor substrate;
a trench arranged in the semiconductor substrate around and between adjacent ones of the plurality of pixel sensors, wherein the trench comprises a shallow region and a deep region underlying the shallow region;
a gap located within the deep region of the trench and between sidewalls of the trench; and
a cap arranged within the trench, wherein a top surface of the cap is arranged under the shallow region and a bottom surface of the cap is arranged over the deep region, wherein the cap is configured to seal the gap, and wherein the cap is formed of a semiconductor material epitaxially grown from surrounding portions of the semiconductor substrate.

2. The image sensor according to claim 1 , further comprising:
a dielectric liner disposed on sidewalls of the shallow region, wherein the dielectric liner has a bottom surface overlying the top surface of the cap; and
a dielectric core laterally disposed between the dielectric liner within the shallow region.

3. The image sensor according to claim 1 , wherein the deep region is lined by a dielectric liner, and wherein the dielectric liner has a top surface underlying the bottom surface of the cap.

4. The image sensor according to claim 1 , wherein the semiconductor substrate is a silicon-on-insulator (SOI) substrate including a first silicon layer and a second silicon layer stacked vertically on opposing sides of an insulating layer, and wherein the trench vertically extends through the second silicon layer to the insulating layer.

5. The image sensor according to claim 1 , wherein the trench extends to a range of between about 7 micrometers and about 10 micrometers into the semiconductor substrate.

6. The image sensor according to claim 1 , wherein a pixel sensor of the plurality of pixel sensors includes a photodetector and a transfer transistor selectively connecting the photodetector to a floating diffusion node (FDN).

7. The image sensor according to claim 1 , wherein the semiconductor substrate is segregated into a core region and a peripheral region by a peripheral isolation region arranged between the core and the peripheral regions, wherein the plurality of pixel sensors are arranged in the core region, and wherein the peripheral region surrounds the core region and includes supporting logic for the image sensor.

8. The image sensor according to claim 1 , wherein a sidewall surface of the cap is laterally offset from a neighboring sidewall surface of the deep region of the trench in a direction extending away from the trench and into the semiconductor substrate.

9. The image sensor according to claim 1 , wherein the cap has a rectangular profile.

10. An image sensor comprising:
a semiconductor substrate having a core region and a peripheral region surrounding the core region;
a peripheral isolation region arranged between the core region and the peripheral region;
pixel sensors arranged over or within the core region;
a trench arranged in the core region around and between the pixel sensors, wherein the trench comprises a shallow region and a deep region underlying the shallow region;
a cap arranged within the trench, between the shallow and deep regions, to seal an air gap in the deep region of the trench, between sidewalls of the trench, wherein the cap is a semiconductor material epitaxially grown from the semiconductor substrate;
a dielectric liner disposed on sidewalls of the shallow region, wherein the dielectric liner has a bottom surface overlying a top surface of the cap; and
an integrated circuit arranged in the peripheral region to support operation of the pixel sensors.

11. The image sensor according to claim 10 , wherein the trench is separated into the shallow region and the deep region by the cap, and wherein the air gap is arranged below the shallow region and laterally between sidewalls of the deep region, and wherein the top surface of the cap is arranged under the shallow region and a bottom surface of the cap is arranged over the deep region.

12. The image sensor according to claim 10 , further comprising:
a dielectric core laterally disposed between the dielectric liner and within the shallow region.

13. The image sensor according to claim 10 , wherein the deep region is lined by a second dielectric liner, and wherein the second dielectric liner has a top surface underlying a bottom surface of the cap.

14. The image sensor according to claim 10 , wherein the semiconductor substrate is a silicon-on-insulator (SOI) substrate, and wherein the trench extends to an insulating layer of the SOI substrate.

15. The image sensor according to claim 10 , wherein one of the pixel sensors comprises a photodetector and a transfer transistor selectively connecting the photodetector to a floating diffusion node (FDN).

16. The image sensor according to claim 10 , wherein the peripheral isolation region includes a second trench that is laterally spaced from the trench and includes a second air gap arranged between sidewalls of the second trench.

17. An image sensor comprising:
a pixel sensor arranged within a semiconductor substrate;
a trench arranged in the semiconductor substrate and laterally surrounding the pixel sensor, wherein the trench comprises a shallow region and a deep region underlying the shallow region; and
a cap sealing a cavity in the deep region of the trench and arranged between the shallow and deep regions of the trench, wherein a sidewall surface of the cap is laterally offset from a neighboring sidewall surface of the deep region of the trench in a direction extending away from the trench and into the semiconductor substrate, and wherein the cap is a semiconductor material.

18. The image sensor according to claim 17 , wherein the cap hermetically seals the cavity.

19. The image sensor according to claim 17 , wherein the cap is an epitaxial layer.

20. The image sensor according to claim 17 , wherein the semiconductor substrate is a silicon-on-insulator (SOI) substrate, and wherein the trench extends to an insulating layer of the SOI substrate.

Assignees

• Taiwan Semiconductor Mfg Co Ltd

Inventors

• Yang Tai-I
• Lin Jung-I
• Lin Ta-Chun
• Lin Tien-Lu
• Wang Chen-Jong

Classifications

• H10W20/077

  on sidewalls or on top surfaces of conductors (H10W20/076 takes precedence) · CPC title

• H10W20/072

  of dielectric parts comprising air gaps · CPC title

• H10W20/46

  comprising air gaps · CPC title

• H10W10/181

  Semiconductor-on-insulator [SOI] isolation regions, e.g. buried oxide regions of SOI wafers · CPC title

• H10W10/0142

  the dielectric materials being chemical transformed from non-dielectric materials · CPC title