Deep trench isolations and methods of forming the same

Patent metadata

Field	Value
Publication number	US-9754993-B2
Application number	US-201514840944-A
Country	US
Kind code	B2
Filing date	Aug 31, 2015
Priority date	Aug 31, 2015
Publication date	Sep 5, 2017
Grant date	Sep 5, 2017

Abstract

A method includes performing an anisotropic etching on a semiconductor substrate to form a trench. The trench has vertical sidewalls and a rounded bottom connected to the vertical sidewalls. A damage removal step is performed to remove a surface layer of the semiconductor substrate, with the surface layer exposed to the trench. The rounded bottom of the trench is etched to form a slant straight bottom surface. The trench is filled to form a trench isolation region in the trench.

First claim

What is claimed is:

1. A method comprising:
performing an anisotropic etching on a semiconductor substrate to form a trench, wherein the trench comprises vertical sidewalls and a rounded bottom connected to the vertical sidewalls;
performing a damage removal step to remove a surface layer of the semiconductor substrate, with the surface layer exposed to the trench, wherein the rounded bottom of the trench is etched to form a slant straight bottom surface; and
filling the trench to form a trench isolation region in the trench.

2. The method of claim 1 further comprising, performing a cleaning on the semiconductor substrate, wherein the rounded bottom remains after the cleaning.

3. The method of claim 1 , wherein after the damage removal step, the trench comprises a vertical upper portion and a U-shaped lower portion connected to the vertical upper portion, with the slant straight bottom surface forming a part of the U-shaped lower portion.

4. The method of claim 1 , wherein after the damage removal step, the trench comprises a vertical upper portion and a V-shaped lower portion connected to the vertical upper portion, with the slant straight bottom surface forming a part of the V-shaped lower portion.

5. The method of claim 1 , wherein the slant straight bottom surface is on a (iii) plane of the semiconductor substrate.

6. The method of claim 1 , wherein the damage removal step is performed using an alkaline-based solution.

7. The method of claim 1 , wherein the filling the trench comprises:
forming a conformal oxide layer extending into the trench; and
forming a conformal high-k dielectric layer over the conformal oxide layer and extending into the trench.

8. The method of claim 7 , wherein the filling the trench further comprises forming a non-conformal high-k dielectric layer over the conformal high-k dielectric layer.

9. The method of claim 7 further comprising:
filling a metal region over the conformal high-k dielectric layer; and
etching back the metal region.

10. The method of claim 1 further comprising:
forming a first plurality of trench isolation regions parallel to the trench isolation region;
forming a second plurality of trench isolation regions perpendicular to the trench isolation region, wherein the first plurality of trench isolation regions and the second plurality of trench isolation regions cross with each other to form a grid; and
forming a pixel unit in the grid.

11. A method comprising:
etching a semiconductor substrate to form a trench;
performing a cleaning on the semiconductor substrate and the trench;
after the cleaning, performing a damage removal step to remove a surface layer of the semiconductor substrate, with the surface layer being in the trench; and
after the damage removal step, filling the trench to form a trench isolation region in the trench, wherein the filling the trench comprises:
forming a dielectric layer extending into the trench;
forming a metal region in the trench and over the dielectric layer; and
etching back the metal region.

12. The method of claim 11 , wherein the cleaning is performed through a first wet etch using a first chemical solution, and the damage removal step is performed through a second wet etch using a second chemical solution, with the second chemical solution different from the first chemical solution.

13. The method of claim 11 , wherein before the damage removal step, the trench comprises vertical sidewalls and a rounded bottom connected to the vertical sidewalls, and after the damage removal step, the rounded bottom is converted to a U-shaped bottom or a V-shaped bottom with straight surfaces.

14. A method comprising:
performing a dry etch on a semiconductor substrate to form a trench extending into the semiconductor substrate, wherein a surface layer of the semiconductor substrate is damaged by the dry etch, and the surface layer is exposed to the trench, and after the dry etch, the trench has rounded bottom surfaces;
performing a wet etch to remove the surface layer of the semiconductor substrate, wherein the wet etch converts the rounded bottom surface into bottom surfaces with straight edges and straight bottoms; and
filling the trench to form a trench isolation region in the trench.

15. The method of claim 14 further comprising, between the dry etch and the wet etch, performing a cleaning on the semiconductor substrate and the trench, wherein after the cleaning, the bottom surface of the trench remains to be rounded.

16. The method of claim 15 , wherein the wet etch causes the bottom surface of the trench to have a U-shape having the straight bottom surface and the straight edges, and wherein the straight edges are slanted.

17. The method of claim 15 , wherein the wet etch causes the bottom surface of the trench to have a V-shape having the straight bottom surface and the straight edges, and wherein the straight edges are slanted.

18. The method of claim 14 , wherein the filling the trench comprises:
depositing a dielectric layer extending into the trench;
after the dielectric layer is formed, filling a metal into a remaining portion of the trench; and
etching back the metal.

19. The method of claim 18 , wherein the filling the trench further comprises:
depositing a high-k dielectric layer over the dielectric layer, wherein the metal is filled over the high-k dielectric layer.

20. The method of claim 18 further comprising etching back the metal.

Assignees

• Taiwan Semiconductor Mfg Co Ltd

Inventors

• Chou Cheng-Hsien
• Tseng Hsiao-Hui
• Lai Chih-Yu
• Chou Shih Pei
• Chiang Yen-Ting
• Tsai Min-Ying

Classifications

• H10W10/0143

  comprising concurrently refilling multiple trenches having different shapes or dimensions · CPC title

• H10W10/17

  formed using trench refilling with dielectric materials, e.g. shallow trench isolations · CPC title

• H10W10/01

  Manufacture or treatment · CPC title

• H10W10/00 Primary

  Isolation regions in semiconductor bodies between components of integrated devices · CPC title

• H01L21/76229

  Electricity · mapped topic