Semiconductor layout in FinFET technologies

Patent metadata

Field	Value
Publication number	US-12450418-B2
Application number	US-202318337781-A
Country	US
Kind code	B2
Filing date	Jun 20, 2023
Priority date	Sep 6, 2017
Publication date	Oct 21, 2025
Grant date	Oct 21, 2025

Abstract

Systems, apparatuses, and methods for placing cells in an integrated circuit are described. In various embodiments, an integrated circuit is divided into many partitions. In a first set of partitions susceptible to transistor latch-up, the many transistor gate stripes are connected to one of the power rails rather than left floating. The lengths of the transistor gate stripes are shortened for well tap cells in the first partition, but increased in a second partition susceptible for poor signal integrity. One or more implant layers are formed underneath the transistor gate stripes in each of the first and second partitions to adjust an amount of protection against transistor latch-up and poor signal integrity. An electrostatic discharge transistor is included with at least one source region of multiple source regions formed in a well with a same doping polarity as the at least one source region.

First claim

What is claimed is:

1. An integrated circuit, comprising:
a plurality of power rails, comprising at least a first power rail and a second power rail, individually connected to different power supplies;
a well formed in a substrate;
one or more active devices formed in the well;
a well tap cell placed adjacent to one of the one or more active devices, wherein:
the well tap cell comprises two high-dopant regions connected to the first power rail with a transistor gate stripe between the two high-dopant regions connected to the second power rail; and
the transistor gate stripe has a first work function less than a second work function of transistor gate stripes of the one or more active devices to increase a decoupling capacitance below the transistor gate stripe between the first power rail and the second power rail.

2. The integrated circuit as recited in claim 1 , wherein the transistor gate stripe comprises a gate material with a doping that adjusts the work function of the transistor gate stripe in a decreasing manner.

3. The integrated circuit as recited in claim 1 , wherein the two high-dopant regions have different doping polarities from one another.

4. The integrated circuit as recited in claim 1 , wherein a length of the transistor gate stripe is greater than a length of transistor gate stripes of the one or more active devices to increase the decoupling capacitance.

5. The integrated circuit as recited in claim 1 , wherein:
the well has an p-type doping polarity;
the first power rail is a ground reference; and
the second power rail connected to the transistor gate stripe is a power supply.

6. The integrated circuit as recited in claim 1 , further comprising an electrostatic discharge (ESD) transistor comprising:
two transistor gate stripes connected to a first terminal;
a plurality of source regions, each connected through a contact to the first terminal; and
a plurality of dummy transistor gate stripes, each connected to a power supply.

7. The integrated circuit as recited in claim 6 , wherein the ESD transistor further comprises two drain regions between the two transistor gate stripes, wherein the two drain regions are connected through contacts to a second terminal different from the first terminal that is connected to an input/output (I/O) pin.

8. A method for semiconductor fabrication, comprising:
forming a well in a substrate;
forming one or more active devices in the well;
forming a plurality of power rails, including at least a first power rail and a second power rail, to provide respective connections to different power supplies;
creating, in an integrated circuit, a well tap cell adjacent to one of the one or more active devices in the well with two high-dopant regions connected to the first power rail with a transistor gate stripe between the two high-dopant regions connected to the second power rail; and
forming the transistor gate stripe with a first work function less than a second work function of transistor gate stripes of the one or more active devices to increase a decoupling capacitance below the transistor gate stripe between the first power rail and the second power rail.

9. The method as recited in claim 8 , further comprising forming the transistor gate stripe with a gate material with a doping that adjusts the work function of the transistor gate stripe in a decreasing manner.

10. The method as recited in claim 8 , further comprising forming the two high-dopant regions with different doping polarities from one another.

11. The method as recited in claim 8 , further comprising forming the transistor gate stripe with a length greater than a length of transistor gate stripes of the one or more active devices to increase the decoupling capacitance.

12. The method as recited in claim 8 , further comprising:
forming the well with an n-type doping polarity;
connecting the first power rail to a power supply; and
connecting, to a ground reference, the second power rail that is connected to the transistor gate stripe.

13. The method as recited in claim 8 , further comprising placing the transistor gate stripe in the integrated circuit in a manner to satisfy density rules of non-planar transistors used to form the one or more active devices formed in the well.

14. The method as recited in claim 8 , further comprising:
forming two transistor gate stripes of an electrostatic discharge (ESD) transistor connected to a first terminal;
forming a plurality of source regions of the ESD transistor, each connected through a contact to the first terminal; and
forming a plurality of dummy transistor gate stripes of the ESD transistor, each connected to a power supply.

15. A system, comprising:
a memory configured to store data; and
a processor configured to process the data, wherein the processor comprises:
a plurality of power rails, comprising at least a first power rail and a second power rail, individually connected to different power supplies;
a well formed in a substrate;
one or more active devices formed in the well;
a well tap cell placed adjacent to one of the one or more active devices, wherein:
the well tap cell comprises two high-dopant regions connected to the first power rail with a transistor gate stripe between the two high-dopant regions connected to the second power rail; and
the transistor gate stripe has a first work function less than a second work function of transistor gate stripes of the one or more active devices to increase a decoupling capacitance below the transistor gate stripe between the first power rail and the second power rail.

16. The system as recited in claim 15 , wherein the transistor gate stripe comprises a gate material with a doping that adjusts the work function of the transistor gate stripe in a decreasing manner.

17. The system as recited in claim 15 , wherein the two high-dopant regions have different doping polarities from one another.

18. The system as recited in claim 15 , wherein a length of the transistor gate stripe is greater than a length of transistor gate stripes of the one or more active devices to increase the decoupling capacitance.

19. The system as recited in claim 15 , wherein:
the well has an p-type doping polarity;
the first power rail is a ground reference; and
the second power rail connected to the transistor gate stripe is a power supply.

20. The system as recited in claim 15 , further comprising an electrostatic discharge (ESD) transistor comprising:
two transistor gate stripes connected to a first terminal;
a plurality of source regions, each connected through a contact to the first terminal; and
a plurality of dummy transistor gate stripes, each connected to a power supply.

Assignees

• Apple Inc

Inventors

• Farbiz Farzan
• Hoffmann Thomas
• Zhang Xin Yi

Classifications

• H10D89/601

  for devices having insulated gate electrodes, e.g. for IGFETs or IGBTs · CPC title

• H10D84/991

  Latch-up prevention · CPC title

• H10D84/907

  CMOS gate arrays · CPC title

• H10D84/854

  comprising arrangements for preventing bipolar actions between the different IGFET regions, e.g. arrangements for latchup prevention · CPC title

• H10D30/62 Primary

  Fin field-effect transistors [FinFET] · CPC title