Circuits and Structures Including Tap Cells and Fabrication Methods Thereof

Patent metadata

Field	Value
Publication number	US-2017194319-A1
Application number	US-201615284678-A
Country	US
Kind code	A1
Filing date	Oct 4, 2016
Priority date	Dec 30, 2015
Publication date	Jul 6, 2017
Grant date	—

Abstract

An example circuit includes: one or more power rails and a tap cell structure. The tap cell structure includes one or more decoupling capacitor cells and one or more tap cells. The one or more tap cells are electrically coupled to the one or more power rails. The one or more decoupling capacitor cells are disposed adjacent to the tap cells and electrically coupled to the one or more power rails.

First claim

What is claimed is:

1 . A circuit comprising:
one or more power rails; and a tap cell structure including one or more decoupling capacitor cells and one or more tap cells, the one or more tap cells being electrically coupled to the one or more power rails, the one or more decoupling capacitor cells being disposed adjacent to the tap cells and electrically coupled to the one or more power rails.

2 . The circuit of claim 1 , wherein the tap cells are placed diagonally from each other in the tap cell structure.

3 . The circuit of claim 1 , wherein the decoupling capacitor cells are placed diagonally from each other in the tap cell structure.

4 . The circuit of claim 1 , wherein a tap cell includes an active region and one or more connection structures, the one or more connection structures coupling the active region to the one or more power rails.

5 . The circuit of claim 1 , wherein the decoupling capacitor cells include one or more conductive materials extending to the tap cells.

6 . The circuit of claim 5 , wherein:
the decoupling capacitor cells include one or more transistors acting as capacitors; and the one or more conductive materials correspond to gate terminals of the one or more transistors.

7 . The circuit of claim 1 , wherein the decoupling capacitor cells include one or more active regions configured to be biased to the one or more power rails.

8 . The circuit of claim 1 , wherein the one or more power rails includes a low-voltage power rail corresponding to an electrical ground and a high-voltage power rail.

9 . The circuit of claim 1 , wherein:
a first tap cell is placed along a first direction adjacent to a first decoupling capacitor cell and along a second direction adjacent to a second decoupling capacitor cell; a second tap cell is placed along the first direction adjacent to the second decoupling capacitor cell and along the second direction adjacent to the first decoupling capacitor cell; the first tap cell is placed diagonally adjacent to the second tap cell; and the first decoupling capacitor cell is placed diagonally adjacent to the second decoupling capacitor cell.

10 . The circuit of claim 9 , wherein:
the first decoupling capacitor cell includes one or more p-type transistors acting as capacitors; and the second decoupling capacitor cell includes one or more n-type transistors acting as capacitors.

11 . The circuit of claim 9 , wherein:
the first decoupling capacitor cell includes one or more n-type transistors acting as capacitors; and the second decoupling capacitor cell includes one or more n-type transistors acting as capacitors.

12 . The circuit of claim 9 , wherein:
the first decoupling capacitor cell includes one or more p-type transistors acting as capacitors; and the second decoupling capacitor cell includes one or more p-type transistors acting as capacitors.

13 . A tap cell structure comprising:
one or more tap cells disposed within a predetermined chip area; one or more decoupling capacitor cells disposed adjacent to the one or more tap cells within the predetermined chip area; and one or more connection structures configured to electrically couple the one or more decoupling capacitor cells to one or more power rails.

14 . The structure of claim 13 , wherein the one or more tap cells include one or more active regions configured to be biased to the one or more power rails.

15 . The structure of claim 13 , wherein the decoupling capacitor cells include one or more conduction materials extending to the tap cells.

16 . The structure of claim 15 , wherein:
the decoupling capacitor cells include one or more transistors acting as capacitors; and the conduction materials correspond to gate terminals of the one or more transistors.

17 . The structure of claim 13 , wherein the decoupling capacitor cells include one or more active regions configured to be biased to the one or more power rails.

18 . The structure of claim 13 , wherein the one or more power rails includes a low-voltage power rail corresponding to an electrical ground and a high-voltage power rail.

19 . The structure of claim 13 , wherein:
a first tap cell is placed along a first direction adjacent to a first decoupling capacitor cell and along a second direction adjacent to a second decoupling capacitor cell; a second tap cell is placed along the first direction adjacent to the second decoupling capacitor cell and along the second direction adjacent to the first decoupling capacitor cell; the first tap cell is placed diagonally adjacent to the second tap cell; and the first decoupling capacitor cell is placed diagonally adjacent to the second decoupling capacitor cell.

20 . A method for manufacturing a tap cell structure, the method comprising:
forming an initial tap cell structure including one or more tap cells, the initial tap cell structure corresponding to a predetermined chip area; forming one or more decoupling capacitor cells adjacent to the one or more tap cells within the predetermined chip area; and forming one or more connection structures for electrically coupling the one or more decoupling capacitor cells to one or more power rails.

Assignees

• Taiwan Semiconductor Mfg Co Ltd

Inventors

• Xu jin-wei
• Chiang Ting-Wei
• Zhuang hui-zhong
• Tien Li-Chun

Classifications

• H10W20/427

  Power or ground buses · CPC title

• H01L23/5286

  Electricity · mapped topic

• H01L27/092

  Electricity · mapped topic

• H01L27/0207

  Electricity · mapped topic

• H01L27/0629 Primary

  Electricity · mapped topic