Gate-coupled NMOS device for electro-static discharge protection

Patent metadata

Field	Value
Publication number	US-9530768-B1
Application number	US-201615208038-A
Country	US
Kind code	B1
Filing date	Jul 12, 2016
Priority date	Feb 12, 2016
Publication date	Dec 27, 2016
Grant date	Dec 27, 2016

Abstract

A gate-coupled NMOS device according to an embodiment includes a P-type well region, an N-type well region, and N-channel MOS transistor, an N+-type tap region, a first conductive layer, and a second conductive layer. The N-type well region surrounds the P-type well region. An inner side of the N-type well region directly contacts a side of the P-type well region. The N-channel MOS transistor is disposed in the P-type well region. The N + -type tap region is disposed in the N-type well region. The first conductive layer is disposed on the N-type well region by interposing a first insulation layer and constitutes a MOS capacitor with the N-type well region and the first insulation layer. The second conductive layer is disposed on the N-type well region by interposing a second insulation layer and constitutes a resistor. A first end portion of the first conductive layer directly contacts a first end portion of the second conductive layer.

First claim

What is claimed is:

1. A gate-coupled NMOS device comprising:
a P-type well region;
an N-type well region surrounding the P-type well region;
an N-channel MOS transistor disposed in the P-type well region;
an N + -type tap region disposed in the N-type well region;
a first conductive layer disposed over the N-type well region by interposing a first insulation layer and constituting a MOS capacitor with the N-type well region and the first insulation layer; and
a second conductive layer disposed over the N-type well region by interposing a second insulation layer and constituting a resistor,
wherein a first end portion of the first conductive layer contacts a first end portion of the second conductive layer.

2. The gate-coupled NMOS device of claim 1 , wherein an inner side of the N-type well region directly contacts a side of the P-type well region.

3. The gate-coupled NMOS device of claim 1 , further comprises:
a deep N-well region surrounding the P-type well region and the N-type well region.

4. The gate-coupled NMOS device of claim 1 , further comprises:
a P + -type contact region disposed in the P-type well region.

5. The gate-coupled NMOS device of claim 4 , further comprises:
an active region disposed in the P-type well region,
wherein the N-channel MOS transistor is disposed in the active region, and
wherein the P + -type contact region is disposed to be spaced apart from the active region and to surrounds the active region.

6. The gate-coupled NMOS device of claim 1 ,
wherein the N + -type tap region is spaced apart from the P-type well region and surrounds the P-type well region.

7. The gate-coupled NMOS device of claim 6 ,
wherein the N + -type tap region has a closed rectangular ring shape.

8. The gate-coupled NMOS device of claim 7 ,
wherein the first insulation layer and the first conductive layer surround first to third sidewalls of the N + -type tap region.

9. The gate-coupled NMOS device of claim 8 ,
wherein inner sidewalls of the first insulation layer and first conductive layer are aligned with an outer sidewall of the N + -type tap region.

10. The gate-coupled NMOS device of claim 8 ,
wherein the second insulation layer and the second conductive layer are disposed in parallel to a fourth sidewall of the N + -type tap region, and
wherein the fourth sidewall is not surrounded by the first insulation layer and the first conductive layer.

11. The gate-coupled NMOS device of claim 6 ,
wherein the N + -type tap region has an opened rectangular ring shape.

12. The gate-coupled NMOS device of claim 11 ,
wherein the first insulation layer and the first conductive layer are surrounded by first to third sidewalls of the N + -type tap region.

13. The gate-coupled NMOS device of claim 12 ,
wherein outer sidewalls of the first insulation layer and the first conductive layer are aligned with an inner side of the N + -type tap region.

14. The gate-coupled NMOS device of claim 12 ,
wherein the second insulation layer and the second conductive layer are disposed in parallel to a fourth sidewall of the N + -type tap region, and
wherein the fourth sidewall is not surrounded by the first insulation layer and the first conductive layer.

15. The gate-coupled NMOS device of claim 1 , wherein a first end portion of the first conductive layer directly contacts a first end portion of the second conductive layer.

16. The gate-coupled NMOS device of claim 1 ,
wherein the first and the second conductive layers have an Integrated structure.

17. The gate-coupled NMOS device of claim 16 ,
wherein each of the first and the second conductive layers includes a polysilicon layer.

18. The gate-coupled NMOS device of claim 1 ,
wherein the second insulation layer is thicker than the first insulation layer.

19. The gate-coupled NMOS device of claim 1 ,
wherein a second end portion of the second conductive layer is spaced apart from a second end portion of the first conductive layer by a predetermined distance.

20. The gate-coupled NMOS device of claim 1 , wherein the N-channel MOS transistors comprise:
a source region and a drain region;
a channel region between the source region and the drain region;
a gate insulation layer disposed over the channel region; and
a gate electrode disposed over the gate insulation layer.

21. The gate-coupled NMOS device of claim 20 ,
wherein the gate electrode and the first conductive layer are coupled to a first node,
wherein the first conductive layer is coupled to the first node at the first end portion through a contact,
wherein the N + -type tap region and the drain region are coupled to an input/output pad,
wherein the second conductive layer is coupled to a ground voltage terminal, and
wherein the second conductive layer is coupled to the ground voltage terminal at a second end portion through the contact.

Assignees

• Sk Hynix Inc

Inventors

• Kim Do Hee

Classifications

• H10D89/921

  characterised by the configuration of the interconnections connecting the protective arrangements, e.g. ESD buses · CPC title

• H10D89/601

  for devices having insulated gate electrodes, e.g. for IGFETs or IGBTs · CPC title

• H10D89/60

  Integrated devices comprising arrangements for electrical or thermal protection, e.g. protection circuits against electrostatic discharge [ESD] · CPC title

• H10D62/151

  of IGFETs  (of IGFETs having LDD or DDD structure H10D30/601; of thin film transistors H10D30/6713) · CPC title

• H10D89/911

  using passive elements as protective elements · CPC title