Semiconductor metal layer structure over cell region

Patent metadata

Field	Value
Publication number	US-12450417-B2
Application number	US-202217856412-A
Country	US
Kind code	B2
Filing date	Jul 1, 2022
Priority date	Mar 2, 2022
Publication date	Oct 21, 2025
Grant date	Oct 21, 2025

Abstract

Metallization structure for an integrated circuit. In one embodiment, an integrated circuit includes a metal-to-diffusion (MD) layer disposed over an active region of a cell, gates disposed over the active region of the cell, and a first metallization layer including M0 tracks disposed over the MD layer and the gates. The integrated circuit further includes a second metallization layer including M1 tracks disposed over the first metallization layer. The M1 tracks include first M1 tracks each having a first predetermined distance from an edge of the cell and second M1 tracks each having a second predetermined distance from the edge of the cell, wherein the first M1 tracks are longer than the second M1 tracks.

First claim

What is claimed is:

1. An integrated circuit, comprising:
a metal-to-diffusion (MD) layer disposed over an active region of a cell;
gates disposed over the active region of the cell;
a first metallization layer including MD tracks disposed over the MD layer and the gates; and
a second metallization layer including M1 tracks disposed over the first metallization layer, wherein the M1 tracks include first M1 tracks each having a first predetermined distance from an edge of the cell and second M1 tracks each having a second predetermined distance from the edge of the cell, and wherein the first M1 tracks are longer than the second M1 tracks.

2. The integrated circuit of claim 1 , wherein the MD layer includes MD tracks arranged to extend along a first direction and spaced from each other in a second direction perpendicular to the first direction.

3. The integrated circuit of claim 2 , wherein the gates are arranged to extend along the first direction and spaced from each other in the second direction to alternate in the second direction with the MD tracks.

4. The integrated circuit of claim 3 , wherein the M0 tracks are arranged to extend along the second direction and spaced from each other in the first direction.

5. The integrated circuit of claim 4 , wherein the M1 tracks are arranged to extend along the first direction and spaced from each other in the second direction.

6. The integrated circuit of claim 5 , wherein the first M1 tracks and the second M1 tracks alternate with each other in the second direction.

7. The integrated circuit of claim 1 , wherein the first predetermined distance between each of the first M1 tracks and the edge of the cell is smaller than the second predetermined distance between each of the second M1 tracks and the edge of the cell.

8. The integrated circuit of claim 7 , further comprising:
first vias to connect one or more the first M1 tracks to the first metallization layer; and
second vias to connect one or more of the second M1 tracks to the first metallization layer,
wherein the first vias are disposed a third predetermined distance from the edge of the cell, the second vias are disposed a fourth predetermined distance from the edge of the cell, and the third predetermined distance is smaller than the fourth predetermined distance.

9. An integrated circuit, comprising:
a first cell,
a second cell abutting the first cell;
a metal-to-diffusion (MD) layer extending over the first cell and the second cell;
gates extending over the first cell and the second cell;
a first metallization layer including MD tracks disposed over the MD layer and the gates; and
a second metallization layer including M1 tracks disposed over the first metallization layer, the M1 tracks including first M1 tracks and second M1 tracks, wherein the first M1 tracks are longer than the second M1 tracks, wherein the first M1 tracks of the first cell align with the second M1 tracks of the second cell, and wherein the second M1 tracks of the first cell align with the first M1 tracks of the second cell.

10. The integrated circuit of claim 9 , wherein the first M1 tracks each have a first predetermined distance from a boundary between the first cell and the second cell, and wherein second M1 tracks each have a second predetermined distance from the boundary.

11. The integrated circuit of claim 10 , wherein the first predetermined distance is smaller than the second predetermined distance.

12. The integrated circuit of claim 9 , wherein:
the MD layer includes MD tracks arranged to extend along a first direction and spaced from each other in a second direction perpendicular to the first direction;
the gates are arranged to extend along the first direction and spaced from each other in the second direction to alternate in the second direction with the MD tracks;
the M0 tracks are arranged to extend along the second direction and spaced from each other in the first direction, and
wherein the M1 tracks are arranged to extend along the first direction and spaced from each other in the second direction.

13. The integrated circuit of claim 12 , wherein the first M1 tracks and the second M1 tracks alternate with each other in the second direction.

14. The integrated circuit of claim 13 , wherein the first M1 tracks align over tracks of the MD layer, and wherein the second M1 tracks align over the gates.

15. A method of forming a cell layout structure, the method comprising:
forming a metal diffusion (MD) layer and gates over an active region of one or more cells;
forming a first metallization layer including MD tracks over the one or more cells; and
forming a second metallization layer including M1 tracks over the first metallization layer, wherein first M1 tracks are disposed a first predetermined distance from an edge of a cell, wherein second M1 tracks are disposed a second predetermined distance from the edge of the cell, wherein the first M1 tracks are longer than the second M1 tracks, and wherein the first predetermined distance is smaller than the second predetermined distance.

16. The method of claim 15 , further comprising:
disposing first vias connected to one or more of the first M1 tracks a third predetermined distance from the edge of the cell, and
disposing second vias connected to one or more of the second M1 tracks a fourth predetermined distance from the edge of the cell, wherein the third predetermined distance is smaller than the fourth predetermined distance.

17. The method of claim 15 , wherein the first M1 tracks and the second M1 tracks alternate with each other in a horizontal direction.

18. The method of claim 17 , wherein the first M1 tracks of a first cell align with the second M1 tracks of a second cell, and wherein the second M1 tracks of the first cell align with the first M1 tracks of the second cell.

19. The method of claim 18 , wherein the first M1 tracks align over tracks of the MD layer, and wherein the second M1 tracks align over the gates.

20. The method of claim 19 , wherein each of the M1 tracks, the tracks of the MD layer, and the gates extend in a vertical direction, and each of the M0 tracks extend in a horizontal direction.

Assignees

• Taiwan Semiconductor Mfg Co Ltd

Inventors

• Chiu Shang-Hsuan
• Chen Chih-Liang
• Zhuang hui-zhong
• Lu Chi-Yu
• Kao Jerry Chang Jui

Classifications

• H10P76/00

  Manufacture or treatment of masks on semiconductor bodies, e.g. by lithography or photolithography · CPC title

• H10P72/50

  for positioning, orientation or alignment · CPC title

• H10W90/00

  Package configurations · CPC title

• H10W72/00

  Interconnections or connectors in packages · CPC title

• H10W29/01

  Manufacture or treatment · CPC title