Advanced node interconnect routing methodology

Patent metadata

Field	Value
Publication number	US-11854974-B2
Application number	US-202117409025-A
Country	US
Kind code	B2
Filing date	Aug 23, 2021
Priority date	Apr 1, 2020
Publication date	Dec 26, 2023
Grant date	Dec 26, 2023

Abstract

One aspect of this description relates to an integrated circuit. In some aspects, the integrated circuit includes a first pattern metal layer, a second pattern metal layer disposed over the first pattern metal layer, wherein the second pattern metal layer includes a second plurality of metal tracks extending in a first direction, and a third pattern metal layer disposed between the first pattern metal layer and the second pattern metal layer, the third pattern metal layer including a first metal track segment and a second metal track segment shifted in a second direction from the first metal track segment, wherein the second plurality of metal tracks, and at least a portion of each of the first metal track segment and the second metal track segment are within a double cell height in the second direction.

First claim

What is claimed is:

1. An integrated circuit comprising:
a first pattern metal layer comprising a plurality of metal tracks extending in a first direction, wherein each of the plurality of metal tracks is separated from its adjacent one of the plurality of metal tracks by a first pitch;
a second pattern metal layer disposed over the first pattern metal layer, wherein the second pattern metal layer comprises a second plurality of metal tracks extending in the first direction and wherein each of the second plurality of metal tracks is separated from its adjacent one of the second plurality of metal tracks by a second pitch;
a third pattern metal layer disposed between the first pattern metal layer and the second pattern metal layer, the third pattern metal layer comprising:
a first metal track segment extending in a second direction perpendicular to the first direction, wherein the first metal track segment is overlapping at least a first one of the plurality of metal tracks of the first pattern metal layer, wherein the first metal track segment has a first edge extending in the first direction;
a second metal track segment extending in the second direction, wherein the second metal track segment is overlapping at least a second one of the plurality of metal tracks of the first pattern metal layer, wherein the second metal track segment has a second edge facing the first edge of the first metal track segment and wherein the second metal track has a third edge opposite the second edge;

wherein the integrated circuit is defined by a double cell height in the second direction and wherein each of the plurality of metal tracks, the second plurality of metal tracks, and at least a portion of each of the first metal track segment and the second metal track segment are within the double cell height.

2. The integrated circuit of claim 1 , wherein the double cell height is less than or equal to 240 nm.

3. The integrated circuit of claim 1 , wherein the first edge of the first metal track segment and the second edge of the second metal track segment are separated by a distance along the second direction, wherein a ratio of the distance and the first pitch is less than or equal to a predetermined threshold.

4. The integrated circuit of claim 3 , wherein the predetermined threshold is 1.

5. The integrated circuit of claim 1 , further comprising:
a pattern via layer disposed between the first pattern metal layer and the third pattern metal layer, the pattern via layer comprising:
a first via coupling the first metal track segment of the third pattern metal layer to the first one of the plurality of metal tracks of the first pattern metal layer; and
a second via coupling the second metal track segment of the third pattern metal layer to the second one of the plurality of metal tracks of the first pattern metal layer.

6. The integrated circuit of claim 5 , wherein the first one of the plurality of metal tracks and the second one of the plurality of metal tracks are configured for signal connection.

7. The integrated circuit of claim 5 , wherein the first one of the plurality of metal tracks is configured for signal connection and the second one of the plurality of metal tracks is configured for power or ground connection.

8. The integrated circuit of claim 7 , wherein the first one of the plurality of metal tracks has a first width less than a second width of the second one of the plurality of metal tracks.

9. The integrated circuit of claim 1 , wherein a plurality of pitches comprises the first pitch for each of the plurality of metal tracks, wherein the plurality of pitches is less than the double cell height.

10. The integrated circuit of claim 1 , further comprising a third metal track segment extending in the second direction, wherein the third metal track segment is overlapping at least a third one of the plurality of metal tracks of the first pattern metal layer, wherein the third metal track segment has a fourth edge facing the third edge of the second metal track segment, wherein the third metal track segment is within the double cell height.

11. The integrated circuit of claim 1 , further comprising:
a pattern poly layer comprising a plurality of poly tracks extending in the second direction, wherein each of the plurality of poly tracks is separated from its adjacent one of the plurality of poly tracks by a poly pitch, wherein each of the second plurality of metal tracks comprises a plurality of metal track segments, wherein at least one of the plurality of metal track segments has a length in the first direction, and wherein a ratio of the length and the poly pitch is less than a second predetermined threshold.

12. The integrated circuit of claim 1 , further comprising:
a fourth pattern metal layer disposed over the second pattern metal layer, wherein the fourth pattern metal layer comprises a fourth metal track segment extending in the second direction, the fourth metal track segment having a length in the second direction, a ratio of the length and the cell height is less than a second predetermined threshold.

13. An integrated circuit comprising:
a first pattern metal layer comprising a plurality of metal tracks extending in a first direction, wherein each of the plurality of metal tracks is separated from its adjacent one of the plurality of metal tracks by a first pitch;
a second pattern metal layer disposed under the first pattern metal layer, the second pattern metal layer comprising:
a first metal track segment extending in a second direction perpendicular to the first direction, wherein the first metal track segment has a first edge extending in the first direction; and
a second metal track segment extending in the second direction, wherein the second metal track segment has a second edge facing the first edge of the first metal track segment and wherein the second metal track has a third edge opposite the second edge;

wherein the integrated circuit is within a pair of standard cells, wherein each of the pair of standard cells are disposed over transistors with effective gate lengths no greater than 2 nanometers.

14. The integrated circuit of claim 13 , further comprising a third pattern metal layer disposed under the second pattern metal layer, the third pattern metal layer comprising a second plurality of metal tracks extending in the first direction, wherein each of the plurality of metal tracks separated from its adjacent one of the plurality of metal tracks by a second pitch.

15. An integrated circuit comprising:
a first pattern metal layer including a plurality of metal tracks extending in a first direction, wherein each of the plurality of metal tracks is separated from its adjacent one of the plurality of metal tracks by a first pitch;
a second pattern metal layer disposed over the first pattern metal layer and including a second plurality of metal tracks extending in the first direction and wherein each of the second plurality of metal tracks is separated from its adjacent one of the second plurality of metal tracks by a second pitch;
a third pattern metal layer disposed between the first pattern metal layer and the second pattern metal layer, the third pattern metal layer comprising:
a first metal track segment extending in a second direction perpendicular to the first direction, wherein the first metal track segment is overlapping at least a first one of the plurality of metal tracks of the first pattern metal layer;
a second metal track segment extending in the second direction, wherein the second metal track segment is overlapping at least a second one of the plurality of metal tracks o

Assignees

• Taiwan Semiconductor Mfg Co Ltd

Inventors

• Peng Shih-Wei
• Tzeng Jiann-Tyng

Classifications

• H10W20/427

  Power or ground buses · CPC title

• H10W20/089

  using processes for implementing desired shapes or dispositions of the openings, e.g. double patterning · CPC title

• H10W20/056

  by filling conductive material into holes, grooves or trenches · CPC title

• H10W20/42

  Vias, e.g. via plugs · CPC title

• H10W20/43

  Layouts of interconnections · CPC title