Integrated circuit and method of manufacturing the same

Patent metadata

Field	Value
Publication number	US-10784869-B2
Application number	US-201916506728-A
Country	US
Kind code	B2
Filing date	Jul 9, 2019
Priority date	Jul 16, 2018
Publication date	Sep 22, 2020
Grant date	Sep 22, 2020

Abstract

An integrated circuit includes a first gate, a second gate, a first contact and a first insulating layer. The first gate extends in the first direction and is located on a first level. The second gate extends in the first direction, is located on the first level, and is separated from the first gate in a second direction different from the first direction. The first contact extends in the second direction, overlaps the first gate and the second gate, is located on a second level different from the first level, and is coupled to at least the first gate. The first insulating layer extends in the second direction, overlaps the first gate and the second gate, and is between the second gate and the first contact.

First claim

What is claimed is:

1. An integrated circuit comprising:
a first active region in a substrate, extending in a first direction, and being located on a first level;
a second active region in the substrate, extending in the first direction, being located on the first level, and being separated from the first active region in a second direction different from the first direction;
a first contact coupled to the first active region, extending in the second direction, being located on a second level different from the first level, and overlapping the first active region;
a second contact coupled to the second active region, extending in the second direction, being located on the second level, overlapping the second active region, and being separated from the first contact in at least the second direction; and
a third contact extending in the second direction, overlapping the first contact and the second contact, being located on a third level different from the first level and the second level, and being coupled to the first active region and the first contact.

2. The integrated circuit of claim 1 , wherein the third contact is further coupled to the second contact and the second active region.

3. The integrated circuit of claim 2 , wherein the integrated circuit is part of an inverter circuit.

4. The integrated circuit of claim 1 , further comprising:
a first conductive structure extending in the first direction, being located on a fourth level different from the first level, the second level and the third level, and overlapping the second contact and the third contact;
a first via between the third contact and the first conductive structure, and the first via coupling the third contact to the first conductive structure; and
an insulating layer extending in the second direction, and being between the second contact and the third contact.

5. The integrated circuit of claim 4 , further comprising:
a third active region in the substrate, extending in the first direction, being located on the first level, and being separated from the second active region in the first direction;
a first gate extending in the second direction, being between the third active region and the second active region, and being located on the second level;
a fourth contact coupled to the third active region, extending in the second direction, being located on the second level, overlapping the third active region, and being separated from the second contact in the first direction;
a fifth contact extending in the second direction, being over the fourth contact, being located on the third level, and being coupled to the third active region; and
a second via between the fifth contact and the first conductive structure, and the second via coupling the fifth contact to the first conductive structure.

6. The integrated circuit of claim 5 , wherein the integrated circuit is part of a NAND logic gate circuit.

7. The integrated circuit of claim 5 , wherein the fourth level is a metal zero (M0) layer of the integrated circuit.

8. The integrated circuit of claim 5 , further comprising:
a fourth active region in the substrate, extending in the first direction, being located on the first level, being separated from the first active region in the first direction, and being separated from the third active region in the second direction;
a sixth contact coupled to the fourth active region, extending in the second direction, being located on the second level, overlapping the fourth active region, and being separated from the first contact in the first direction;
a seventh contact extending in the second direction, being over the sixth contact, being located on the third level, and being coupled to the fourth active region;
a second conductive structure extending in the first direction, being located on the fourth level, and overlapping the sixth contact and the seventh contact; and
a third via between the seventh contact and the second conductive structure, and the third via coupling the seventh contact to the second conductive structure.

9. The integrated circuit of claim 8 , further comprising:
a fifth active region in the substrate, extending in the first direction, being located on the first level, being separated from the first active region in the first direction;
a second gate extending in the second direction, being between the first active region and the fifth active region, and being located on the second level;
an eighth contact coupled to the fifth active region, extending in the second direction, being located on the second level, overlapping the fifth active region, and being separated from the first contact in the first direction;
a ninth contact extending in the second direction, being over the eighth contact, being located on the third level, and being coupled to the fifth active region; and
a fourth via between the ninth contact and the second conductive structure, and the fourth via coupling the ninth contact to the second conductive structure.

10. The integrated circuit of claim 9 , wherein the integrated circuit is part of an AND OR INVERTER logic circuit.

11. An integrated circuit comprising:
a first gate extending in a first direction, being located on a first level;
a second gate extending in the first direction, being located on the first level, and being separated from the first gate in a second direction different from the first direction;
a first gate portion extending in the second direction, overlapping the first gate and the second gate, being located on a second level different from the first level, and being coupled to at least the first gate; and
a first insulating layer extending in the second direction, overlapping the second gate, and being between the second gate and the first gate portion.

12. The integrated circuit of claim 11 , further comprising:
a third gate extending in the first direction, being located on the first level, and being separated from the second gate in the first direction;
a first conductive structure extending in the first direction, being located on a third level different from the first level and the second level, and overlapping the third gate and the first gate portion;
a first via between the first gate portion and the first conductive structure, and the first via coupling the first gate portion to the first conductive structure; and
a second via between the third gate and the first conductive structure, and the second via coupling the third gate to the first conductive structure.

13. The integrated circuit of claim 12 , further comprising:
a first active region in a substrate, extending in the first direction, being located on a fourth level different from the first level, the second level and the third level;
a second active region in the substrate, extending in the first direction, being located on the fourth level, and being separated from the first active region in the second direction;
a first contact coupled to the first active region and the second active region, extending in the second direction, being located on the first level, and overlapping the first active region and the second active region, and being separated from the third gate in the first direction; and
a second contact extending in the second direction, and overlapping at least a portion of the first contact, being located on the second level.

14. The integrated circuit of claim 13 , further comprising:
a second insulating layer extending in the second direction, and being between the second contact and the portion of the first contact; and
a third via between the second contact and the first conductive st

Assignees

• Taiwan Semiconductor Mfg Co Ltd

Inventors

• Peng Shih-Wei
• Chuang Cheng-Chi
• Lai Chih-Ming
• Tzeng Jiann-Tyng
• Lin Wei-Cheng

Classifications

• H10W20/43

  Layouts of interconnections · CPC title

• H10W20/42

  Vias, e.g. via plugs · CPC title

• H10D84/01

  Manufacture or treatment · CPC title

• H10D84/00

  Integrated devices formed in or on semiconductor substrates that comprise only semiconducting layers, e.g. on Si wafers or on GaAs-on-Si wafers · CPC title

• H10D84/0165

  the components including complementary IGFETs, e.g. CMOS devices · CPC title