Integrated circuit layout method and device

Patent metadata

Field	Value
Publication number	US-10741540-B2
Application number	US-201816204678-A
Country	US
Kind code	B2
Filing date	Nov 29, 2018
Priority date	Jun 29, 2018
Publication date	Aug 11, 2020
Grant date	Aug 11, 2020

Abstract

A method of generating a layout diagram of an IC cell includes defining a boundary recess in a boundary of the cell by extending a first portion of the boundary along a first direction, extending a second portion of the boundary away from the first portion in a second direction perpendicular to the first direction, the second portion being contiguous with the first portion, and extending a third portion of the boundary away from the first portion in the second direction, the third portion being contiguous with the first portion. An active region is positioned in the cell by extending the active region away from the first portion in a third direction opposite to the second direction. The layout diagram is stored on a non-transitory computer-readable medium.

First claim

What is claimed is:

1. A method of generating a layout diagram of an integrated circuit (IC) cell, the IC layout diagram being stored on a non-transitory computer-readable medium, the method comprising:
defining a boundary recess in a boundary of the cell by:
extending a first portion of the boundary along a first direction;
extending a second portion of the boundary away from the first portion in a second direction perpendicular to the first direction, the second portion being contiguous with the first portion; and
extending a third portion of the boundary away from the first portion in the second direction, the third portion being contiguous with the first portion; and

positioning an active region in the cell by extending the active region away from the first portion in a third direction opposite to the second direction.

2. The method of claim 1 , further comprising fabricating, based on the IC layout diagram, at least one of:
one or more semiconductor masks, or
at least one component in a layer of a semiconductor IC.

3. The method of claim 1 , wherein
the active region is a first active region of a plurality of active regions in the cell, and
the method further comprises positioning a second active region of the plurality of active regions by extending the second active region away from the first portion in the third direction.

4. The method of claim 3 , wherein
the positioning the first active region of the plurality of active regions comprises including the first active region of the plurality of active regions in a PMOS device, and
the positioning the second active region of the plurality of active regions comprises including the second active region of the plurality of active regions in an NMOS device.

5. The method of claim 1 , wherein
the active region is a first active region of a plurality of active regions in the cell, each active region of the plurality of active regions extending in the third direction, and
the method further comprises positioning a second active region of the plurality of active regions and a third active region of the plurality of active regions by aligning the second active region of the plurality of active regions, the third active region of the plurality of active regions, the second portion, and the third portion along the first direction.

6. The method of claim 5 , wherein
the positioning the second active region of the plurality of active regions comprises including the second active region of the plurality of active regions in a PMOS device, and
the positioning the third active region of the plurality of active regions comprises including the third active region of the plurality of active regions in an NMOS device.

7. The method of claim 1 , wherein the defining the boundary recess in the boundary of the cell comprises defining a boundary protrusion in the boundary by:
extending a fourth portion of the boundary in the first direction;
extending a fifth portion of the boundary away from the fourth portion in the second direction, the fifth portion being contiguous with the fourth portion; and
extending a sixth portion away from the fourth portion in the second direction, the sixth portion being contiguous with the fourth portion,
wherein the active region is between the first portion and the fourth portion.

8. The method of claim 7 , wherein
the active region is a first active region of a plurality of active regions in the cell, each active region of the plurality of active regions extending in the third direction,
the defining the boundary recess in the boundary of the cell further comprises extending a seventh portion of the boundary in the second direction, the seventh portion being non-contiguous with the fourth portion and parallel to the fifth portion and the sixth portion, and
the method further comprises positioning a second active region of the plurality of active regions by aligning the first active region of the plurality of active regions, the second active region of the plurality of active regions, the fifth portion, the sixth portion, and the seventh portion in the first direction.

9. The method of claim 8 , wherein
one of the positioning the first active region of the plurality of active regions or the positioning the second active region of the plurality of active regions comprises including the one of the first active region of the plurality of active regions or the second active region of the plurality of active regions in a PMOS device, and
the other of the positioning the first active region of the plurality of active regions or the positioning the second active region of the plurality of active regions comprises including the other of the first active region of the plurality of active regions or the second active region of the plurality of active regions in an NMOS device.

10. A method of generating a layout diagram of an integrated circuit (IC), the IC layout diagram being stored on a non-transitory computer-readable medium, the method comprising:
abutting a first cell of the IC layout diagram with a second cell of the IC layout diagram by:
fitting a boundary protrusion of a boundary of the first cell within a boundary recess of a boundary of the second cell, and
intersecting a first gate region of the IC layout diagram with the boundary protrusion and with a first active region of the second cell.

11. The method of claim 10 , further comprising performing one or more lithographic exposures based on the IC layout diagram.

12. The method of claim 10 , wherein the intersecting the first gate region of the IC layout diagram with the boundary protrusion and with the first active region comprises aligning the first cell and the second cell based on a gate track.

13. The method of claim 10 , wherein the intersecting the first gate region of the IC layout diagram with the boundary protrusion and with the first active region comprises intersecting the first gate region with a second active region of the second cell.

14. The method of claim 10 , wherein
the boundary protrusion of the first cell is a first boundary protrusion of a plurality of boundary protrusions of the first cell, and
the intersecting the first gate region of the IC layout diagram with the boundary protrusion and with the first active region comprises intersecting the first gate region with a second boundary protrusion of the plurality of boundary protrusions.

15. The method of claim 10 , further comprising positioning the first cell and the second cell within a place-and-route boundary.

16. An integrated circuit (IC) device comprising:
a plurality of active areas, each active area of the plurality of active areas extending in a first direction; and
a first gate structure extending in a second direction perpendicular to the first direction, the first gate structure overlying each active area of the plurality of active areas,
wherein
a first active area of the plurality of active areas is between a second active area of the plurality of active areas and a third active area of the plurality of active areas,
the first gate structure overlies an edge of the first active area of the plurality of active areas, and
each of the second active area of the plurality of active areas and the third active area of the plurality of active areas extends across the first gate structure.

17. The IC device of claim 16 , further comprising:
a second gate structure extending in the second direction, the second gate structure overlying each active area of the plurality of active areas,
wherein
the second gate structure ove

Assignees

• Taiwan Semiconductor Mfg Co Ltd
• Taiwan Semiconductor Manufacutring Company Ltd

Inventors

• Chen Chien-Ying
• Lu Lee-Chung
• Tien Li-Chun
• Guo Ta-Pen

Classifications

• H10D84/85

  Complementary IGFETs, e.g. CMOS · CPC title

• H10D84/00

  Integrated devices formed in or on semiconductor substrates that comprise only semiconducting layers, e.g. on Si wafers or on GaAs-on-Si wafers · CPC title

• H10D84/0165

  the components including complementary IGFETs, e.g. CMOS devices · CPC title

• H10D89/10 Primary

  Integrated device layouts · CPC title

• G06F30/392

  Floor-planning or layout, e.g. partitioning or placement · CPC title