Semiconductor device

Patent metadata

Field	Value
Publication number	US-12444697-B2
Application number	US-202418612304-A
Country	US
Kind code	B2
Filing date	Mar 21, 2024
Priority date	Dec 1, 2020
Publication date	Oct 14, 2025
Grant date	Oct 14, 2025

Abstract

A semiconductor device may include a substrate including a first region and a second region and a first active pattern on the first region. The first active pattern may include a pair of first source/drain patterns and a first channel pattern therebetween, and the first channel pattern may include a plurality of first semiconductor patterns stacked on the substrate. The semiconductor device may further include a first gate electrode, which is provided on the first channel patterns, and a supporting pattern, which is provided on side surfaces of the plurality of first semiconductor patterns to connect the side surfaces of the plurality of first semiconductor patterns to each other.

First claim

What is claimed is:

1. A semiconductor device, comprising:
a substrate including a first region and a second region;
a first active pattern on the first region, the first active pattern comprising a pair of first source/drain patterns and a first channel pattern therebetween, the first channel pattern comprising a plurality of first semiconductor patterns stacked on the substrate;
a first gate electrode provided on the first channel pattern; and
a supporting pattern being configured to connect the plurality of first semiconductor patterns therebetween, wherein the supporting pattern is separated from each of the pair of first source/drain patterns.

2. The semiconductor device of claim 1 ,
wherein the supporting pattern comprises the same material as the plurality of first semiconductor patterns.

3. The semiconductor device of claim 1 , further comprising:
a second active pattern and a second gate electrode provided on the second region,
wherein the second active pattern comprises a pair of second source/drain patterns and a second channel pattern therebetween,
wherein the second channel pattern comprises a plurality of second semiconductor patterns stacked on the substrate,
wherein the second gate electrode is provided on the second channel pattern, and
wherein a length of the first channel pattern is larger than a length of the second channel pattern.

4. A semiconductor device, comprising:
a substrate including a first region and a second region;
a first active pattern on the first region, the first active pattern comprising a pair of first source/drain patterns and a first channel pattern therebetween, the first channel pattern comprising a plurality of first semiconductor patterns stacked on the substrate;
a second active pattern on the second region, the second active pattern comprising a pair of second source/drain patterns and a second channel pattern therebetween, the second channel pattern comprising a plurality of second semiconductor patterns stacked on the substrate;
supporting patterns configured to connect the plurality of first semiconductor patterns; and
a first gate electrode and a second gate electrode provided on the first and second channel patterns, respectively,
wherein a length of the first channel pattern is larger than a length of the second channel pattern, and
wherein the plurality of first semiconductor patterns include a first material and the supporting patterns include the first material.

5. The semiconductor device of claim 4 ,
wherein the supporting patterns and the plurality of first semiconductor patterns are connected to form a single object.

6. The semiconductor device of claim 4 ,
wherein the first gate electrode covers the supporting patterns, and
wherein the semiconductor device further comprises a gate insulating layer between the first gate electrode and the supporting patterns.

7. The semiconductor device of claim 4 ,
wherein the plurality of first semiconductor patterns and the supporting patterns have the same crystal direction.

8. The semiconductor device of claim 4 ,
wherein the supporting patterns comprise amorphous silicon.

9. A semiconductor device, comprising:
a substrate including a first region and a second region;
a device isolation layer defining a first active region on the first region and a second active region on the second region;
a pair of first source/drain patterns and a pair of second source/drain patterns on the first active region and the second active region, respectively;
a first channel pattern between the pair of first source/drain patterns;
a second channel pattern between the pair of second source/drain patterns, each of the first and second channel patterns comprising first to third semiconductor patterns sequentially stacked on the substrate;
a first gate electrode and a second gate electrode on the first channel pattern and the second channel pattern, respectively;
a first gate insulating layer between the first channel pattern and the first gate electrode;
a second gate insulating layer between the second channel pattern and the second gate electrode;
a pair of gate spacers provided at opposite sides of each of the first and second gate electrodes;
a gate capping pattern on a top surface of each of the first and second gate electrodes;
a pair of first active contacts electrically connected to the pair of first source/drain patterns;
a pair of second active contacts electrically connected to the pair of second source/drain patterns;
first and second gate contacts electrically connected to the first and second gate electrodes;
a first metal layer on the pair of first active contacts, the pair of second active contacts, and the first and second gate contacts, the first metal layer comprising first interconnection lines electrically connected to the pair of first active contacts, the pair of second active contacts, and the first and second gate contacts;
a second metal layer on the first metal layer; and
a first supporting pattern connecting the first to third semiconductor patterns of the first channel pattern and contacting the first to third semiconductor patterns thereof.

10. The semiconductor device of claim 9 , further comprising:
a second supporting pattern that connects the first to third semiconductor patterns of the first channel pattern and is in contact with the first to third semiconductor patterns thereof,
wherein the first supporting pattern and the second supporting pattern are spaced apart from each other.

11. The semiconductor device of claim 9 ,
wherein the first supporting pattern comprises silicon, which has the same crystal direction as the first to third semiconductor patterns of the first channel pattern or has an amorphous structure.

Assignees

• Samsung Electronics Co Ltd

Inventors

• Park Noh Yeong
• Park Beomjin
• Bae Dong Il
• Baek Sangwon
• Song Hyun-Seung

Classifications

• H10P14/3452

  Microstructure · CPC title

• H10W42/121 Primary

  protecting against mechanical damage (H10W76/00, H10W74/00 take precedence) · CPC title

• H10D84/0167 Primary

  Manufacturing their channels · CPC title

• H10D84/85

  Complementary IGFETs, e.g. CMOS · CPC title

• H10D84/038

  using silicon technology, e.g. SiGe · CPC title