Support for long channel length nanowire transistors

Patent metadata

Field	Value
Publication number	US-9627330-B2
Application number	US-201514798007-A
Country	US
Kind code	B2
Filing date	Jul 13, 2015
Priority date	Jul 13, 2015
Publication date	Apr 18, 2017
Grant date	Apr 18, 2017

Abstract

A nanowire device includes a first component formed on a substrate and a second component disposed apart from the first component on the substrate. A nanowire is configured to connect the first component to the second component. An anchor pad is formed along a span of the nanowire and configured to support the nanowire along the span to prevent sagging.

First claim

The invention claimed is:

1. A nanowire device, comprising:
a first region formed on a substrate;
a second region disposed apart from the first region on the substrate;
at least one nanowire configured to connect the first region to the second region; and
a plurality of anchor pads, as portions of the at least one nanowire, formed along a span of the at least one nanowire and configured to support the at least one nanowire along the span to prevent sagging, wherein adjacent anchor pads of the plurality of anchor pads are separated by a distance of between about 50 nm to about 300 nm.

2. The nanowire device as recited in claim 1 , wherein the first region includes a transistor source and the second region includes a transistor drain, and the at least one nanowire forms a channel of the nanowire device.

3. The nanowire device as recited in claim 2 , further comprising a gate dielectric and gate conductor formed around a nanowire segment of the at least one nanowire.

4. The nanowire device as recited in claim 1 , wherein the at least one nanowire and the plurality of anchor pads include a semiconductor material.

5. The nanowire device as recited in claim 1 , wherein the at least one nanowire is a plurality of parallel nanowires, wherein each of the plurality of parallel nanowires is supported along the span by each of the plurality of anchor pads.

6. The nanowire device as recited in claim 1 , wherein each of the anchor pads has a pad width of between about 20 nm and about 50 nm.

7. The nanowire device as recited in claim 1 , wherein the at least one nanowire includes a plurality of nanowire segments connected by a plurality of anchor pads.

8. The nanowire device as recited in claim 7 , wherein the plurality of nanowire segments and the plurality of anchor pads form a device channel having a length of between 500 nm to about 2 microns.

9. A nanowire device, comprising:
a source and a drain formed on a substrate and separated by a span;
at least one nanowire, including a plurality of anchor pads and a plurality of nanowire segments, suspended over the substrate and configured to connect the source and the drain as a channel;
a gate dielectric and a gate metal formed around each nanowire segment of the at least one nanowire; and
adjacent anchor pads of the plurality of anchor pads, formed along the span and configured to support the at least one nanowire along the span to prevent sagging, separated by a distance of between about 50 nm to about 300 nm.

10. The nanowire device as recited in claim 9 , wherein the at least one nanowire with the plurality of anchor pads include a semiconductor material.

11. The nanowire device as recited in claim 9 , wherein the at least one nanowire is a plurality of parallel nanowires, wherein each of the plurality of parallel nanowires is supported along the span by each of the plurality of anchor pads.

12. The nanowire device as recited in claim 9 , wherein each of the anchor pads has a pad width of between about 20 nm and about 50 nm.

13. The nanowire device as recited in claim 9 , wherein in the at least one nanowire the plurality of nanowire segments are connected by the plurality of anchor pads.

14. The nanowire device as recited in claim 13 , wherein the plurality of nanowire segments and the plurality of anchor pads form a device channel having a length of between 500 nm to about 2 microns.

Assignees

• IBM

Inventors

• Balakrishnan Karthik
• Lauer Isaac
• Yamashita Tenko
• Sleight Jeffrey W

Classifications

• H10P14/3462

  Nanowires · CPC title

• H10P14/2914

  Oxides · CPC title

• H10W42/121 Primary

  protecting against mechanical damage (H10W76/00, H10W74/00 take precedence) · CPC title

• B82Y10/00

  Nanotechnology for information processing, storage or transmission, e.g. quantum computing or single electron logic · CPC title

• H01L29/78696

  Electricity · mapped topic