Method of forming a single-crystal nanowire finFET

Patent metadata

Field	Value
Publication number	US-9871102-B2
Application number	US-201514684443-A
Country	US
Kind code	B2
Filing date	Apr 13, 2015
Priority date	Mar 13, 2015
Publication date	Jan 16, 2018
Grant date	Jan 16, 2018

Abstract

A semiconductor device and a method of forming the same, the semiconductor device includes a single crystal substrate, a source/drain structure and a nanowire structure. The source/drain structure is disposed on and contacts with the substrate. The nanowire structure is connected to the source/drain structure.

First claim

What is claimed is:

1. A method of forming a semiconductor device, comprising:
forming two dielectric layers and two first material layers stacked alternately on a substrate;
etching the first material layers and the dielectric layers to expose a portion of the substrate;
forming a second material layer on the portion of the substrate;
transforming the first material layers into two single-crystal material layers; and
completely removing the dielectric layer between the two single-crystal material layers and partially removing the dielectric layer between the single-crystal material layers and the substrate to leave a portion of the dielectric remained on the substrate and not in contact with the two single-crystal material layers, and to form a nanowire structure.

2. The method of forming a semiconductor device according to claim 1 , further comprising:
patterning the first material layers before the transforming of the first material layers.

3. The method of forming a semiconductor device according to claim 1 , further comprising:
patterning the first material layers after the transforming of the first material layers.

4. The method of forming a semiconductor device according to claim 1 , wherein the transforming of the first material layers is performed through a thermal process or a laser irradiation process.

5. The method of forming a semiconductor device according to claim 1 , wherein the second material layer directly contacts the portion of the substrate.

6. The method of forming a semiconductor device according to claim 1 , wherein the portion of the substrate comprises a source/drain region or a supporting region.

7. The method of forming a semiconductor device according to claim 1 , further comprising:
performing an anti-punch through implantation process at the portion of the substrate.

8. The method of forming a semiconductor device according to claim 1 , further comprising:
forming a gate electrode at least partially surrounding the nanowire structure; and
forming a gate dielectric layer between the gate electrode and the nanowire structure.

9. The method of forming a semiconductor device according to claim 8 , wherein before the forming of the gate dielectric layer further comprises:
performing an annealing process to round the nanowire structure.

10. The method of forming a semiconductor device according to claim 1 , wherein the first material layers and the second material layer comprise different materials, or the first material layers and the substrate comprise different materials.

11. The method of forming a semiconductor device according to claim 1 , wherein the second material layer is formed through a low temperature epitaxial process.

Assignees

• United Microelectronics Corp

Inventors

• Chen Hsin-Yu
• Chiang Huai-Tzu
• Lin Sheng-Hao
• Lee Hao-Ming

Classifications

• H10P95/906

  for altering the shape of semiconductors, e.g. smoothing the surface · CPC title

• H10P14/3802

  Crystallisation or recrystallisation of non-monocrystalline semiconductor materials, e.g. regrowth · CPC title

• H10P14/3411

  Silicon, silicon germanium or germanium · CPC title

• B82Y10/00

  Nanotechnology for information processing, storage or transmission, e.g. quantum computing or single electron logic · CPC title

• H01L29/0649

  Electricity · mapped topic