Structures and methods for long-channel devices in nanosheet technology

Patent metadata

Field	Value
Publication number	US-9947743-B2
Application number	US-201615184520-A
Country	US
Kind code	B2
Filing date	Jun 16, 2016
Priority date	Jun 16, 2016
Publication date	Apr 17, 2018
Grant date	Apr 17, 2018

Abstract

Techniques for providing supporting structures for suspended nanosheets/wires in long-channel devices are provided. In one aspect, a method of forming a device structure includes: forming a series of alternating active and sacrificial layers as a stack on a substrate; patterning at least one feature through each of the active and sacrificial layers in the stack; filling the feature with a fill material that is resistant to etching performed on the sacrificial layers; and etching the sacrificial layers to selectively remove at least a portion of each of the sacrificial layers from the stack thereby suspending the active layers, wherein following the etching the fill material remains as a structure supporting the suspended active layers. Transistor devices and methods for formation thereof are also provided.

First claim

What is claimed is:

1. A method of forming a device structure, the method comprising:
forming a series of alternating active and sacrificial layers as a stack on a substrate;
patterning at least one feature through each of the active and sacrificial layers in the stack, wherein the active layers comprise a channel material and serve as a channel region between a source and a drain, and wherein the feature is patterned through only a middle of each of the active layers with the channel material fully surrounding the feature in each of the active layers such that current flow through the channel region is uninterrupted by the feature patterned through each of the active layers;
filling the feature with a fill material that is resistant to etching performed on the sacrificial layers; and
etching the sacrificial layers within the channel region to selectively remove the sacrificial layers from between the active layers in the channel region thereby suspending the active layers, wherein following the etching the fill material remains as a structure supporting the suspended active layers.

2. The method of claim 1 , wherein the active layers comprise silicon and the sacrificial layers comprise silicon germanium.

3. The method of claim 1 , wherein the active layers comprise silicon germanium and the sacrificial layers comprise silicon.

4. The method of claim 1 , wherein the feature comprises a pinhole.

5. The method of claim 4 , wherein the pinhole has a diameter d of from about 5 nanometers to about 15 nanometers, and ranges therebetween.

6. The method of claim 1 , wherein the feature comprises a trench.

7. The method of claim 6 , wherein the trench has a width w of from about 5 nanometers to about 15 nanometers, and ranges therebetween.

8. The method of claim 1 , wherein the fill material comprises a same material as the active layers.

9. The method of claim 1 , wherein the fill material comprises an insulator.

10. The method of claim 9 , wherein the insulator is an oxide.

11. The method of claim 1 , further comprising:
forming a hardmask on the stack patterned with the footprint and location of the feature.

12. A method of forming a transistor device, comprising:
forming a series of alternating active and sacrificial layers as a stack on a substrate;
patterning at least one feature through each of the active and sacrificial layers in the stack;
filling the feature with a fill material that is resistant to etching performed on the sacrificial layers;
forming a dummy gate over a portion of the stack that serves as a channel region of the transistor device;
forming source and drain regions on opposite sides of the dummy gate;
burying the dummy gate in a gap fill dielectric;
removing the dummy gate forming a gate trench in the gap fill dielectric;
etching the sacrificial layers within the gate trench to selectively remove the sacrificial layers from between the active layers in the channel region thereby suspending the active layers in the channel region of the transistor device, wherein following the etching the fill material remains as a structure supporting the suspended active layers in the gate trench; and
forming a replacement gate in the gate trench.

13. The method of claim 12 , further comprising:
forming dummy gate spacers on opposite sides of the dummy gate.

14. The method of claim 12 , wherein the active layers comprise silicon and the sacrificial layers comprise silicon germanium.

15. The method of claim 12 , wherein the active layers comprise silicon germanium and the sacrificial layers comprise silicon.

16. The method of claim 12 , wherein the feature comprises a pinhole.

17. The method of claim 12 , wherein the feature comprises a trench.

18. The method of claim 12 , wherein the fill material comprises a same material as the active layers.

19. The method of claim 12 , wherein the fill material comprises an insulator.

Assignees

• IBM

Inventors

• Doris Bruce B
• Hook Terence B

Classifications

• H01L29/6656

  Electricity · mapped topic

• H01L29/78642

  Electricity · mapped topic

• H01L29/4236

  Electricity · mapped topic

• H01L29/66545

  Electricity · mapped topic

• H01L29/42392

  Electricity · mapped topic