Silicon-on-insulator die support structures and related methods

Patent metadata

Field	Value
Publication number	US-12444609-B2
Application number	US-202217806144-A
Country	US
Kind code	B2
Filing date	Jun 9, 2022
Priority date	Aug 17, 2017
Publication date	Oct 14, 2025
Grant date	Oct 14, 2025

Abstract

Implementations of a silicon-in-insulator (SOI) semiconductor die may include a first largest planar surface, a second largest planar surface and a thickness between the first largest planar surface and the second largest planar surface; and one of a permanent die support structure, a temporary die support structure, or any combination thereof coupled to one of the first largest planar surface, the second largest planar surface, the thickness, or any combination thereof. The first largest planar surface, the second largest planar surface, and the thickness may be included through a silicon layer coupled to a insulative layer.

First claim

What is claimed is:

1. A silicon-in-insulator (SOI) semiconductor die comprising:
a first largest planar surface, a second largest planar surface and a thickness between the first largest planar surface and the second largest planar surface; and
a permanent die support structure and a temporary die support structure directly coupled to one of the first largest planar surface, the second largest planar surface, the thickness, or any combination thereof;
wherein the first largest planar surface, the second largest planar surface, and the thickness are formed of a conductive layer directly coupled onto a silicon layer and an insulative layer coupled over the conductive layer.

2. The die of claim 1 , wherein a warpage of one of the first largest planar surface or the second largest planar surface is less than 200 microns.

3. The die of claim 1 , wherein the conductive layer comprises titanium.

4. The die of claim 1 , wherein the conductive layer is patterned.

5. The die of claim 1 , wherein the permanent die support structure comprises a mold compound.

6. The die of claim 1 , further comprising a third die support structure coupled to one of the first largest planar surface, the second largest planar surface, the thickness, or any combination thereof.

7. A silicon-in-insulator (SOI) semiconductor die comprising:
a first largest planar surface, a second largest planar surface and a thickness between the first largest planar surface and the second largest planar surface; and
a permanent die support structure and a temporary die support structure directly coupled to the first largest planar surface;
wherein the first largest planar surface, the second largest planar surface, and the thickness are formed by a silicon layer and an insulative layer coupled over the silicon layer; and
wherein one of the permanent die support structure or temporary die support structure is directly coupled to both the insulative layer and the silicon layer.

8. The die of claim 7 , wherein a warpage of one of the first largest planar surface or the second largest planar surface is less than 200 microns.

9. The die of claim 7 , wherein the thickness is between 0.1 microns and 125 microns.

10. The die of claim 7 , wherein a perimeter of the SOI semiconductor die is rectangular and a size of the SOI semiconductor die is at least 6 mm by 6 mm.

11. The die of claim 7 , wherein the permanent die support structure comprises a mold compound.

Assignees

• Semiconductor Components Ind Llc

Inventors

• Seddon Michael J
• Carney Francis J
• Kurose Eiji
• Chew Chee Hiong
• Wang Soon Wei

Classifications

• H10W72/0198

  batch processes · CPC title

• H10W72/944

  Dispositions of multiple bond pads · CPC title

• H10W72/952

  comprising metals or metalloids, e.g. PbSn, Ag or Cu · CPC title

• H10W72/923

  Bond pads having multiple stacked layers · CPC title

• H10W72/29

  Bond pads specially adapted therefor · CPC title