Display substrate, display device and motherboard

Patent metadata

Field	Value
Publication number	US-12443082-B2
Application number	US-202218702386-A
Country	US
Kind code	B2
Filing date	Oct 25, 2022
Priority date	Oct 25, 2022
Publication date	Oct 14, 2025
Grant date	Oct 14, 2025

Abstract

The display substrate, display device and motherboard provided in the present disclosure include a first base substrate, a plurality of first signal lines, a plurality of second signal lines, and a plurality of pixel electrodes, and the orthographic projection of the pixel electrodes on the first base substrate is within the orthographic projection of the area defined by the intersection of each first signal line and each second signal line; first light-shielding structures are located above the layer where the pixel electrodes are located, each first light-shielding structure extends in the second direction and is arranged along the first direction, the orthographic projections of the first light-shielding structures on the substrate of the first substrate is within the orthographic projection of gaps between the columns of pixel electrodes extending in the second direction, and has an area that does not overlap with the orthographic projection of the second signal line.

First claim

What is claimed is:

1. A display substrate comprising:
a first base substrate;
a plurality of first signal lines on a side of the first base substrate, wherein the plurality of first signal lines extend along a first direction and are arranged along a second direction, and the first direction and the second direction intersect with each other;
a plurality of second signal lines on the same side of the first base substrate as the plurality of first signal lines, wherein the plurality of second signal lines and the plurality of first signal lines are arranged in different layers, and the plurality of second signal lines extend along the second direction and are arranged along the first direction;
a plurality of pixel electrodes on a side, facing away from the first base substrate, of layers where the plurality of first signal lines and the plurality of second signal lines are located, wherein orthographic projections of the plurality of pixel electrodes on the first base substrate are within areas defined by intersections of orthographic projections of the plurality of first signal lines on the first base substrate and orthotropic projections of the plurality of second signal lines on the first base substrate;
a plurality of first light-shielding structures on a side, facing away from the first base substrate, of a layer where the plurality of pixel electrodes are located, wherein the plurality of first light-shielding structures extend along the second direction and are arranged along the first direction, orthographic projections of the plurality of first light-shielding structures on the first base substrate are within orthographic projection of a gaps between columns of pixel electrodes extending in the second direction on the first base substrate, the orthographic projections of the plurality of first light-shielding structures on the first base substrate and the orthographic projections of the plurality of second signal lines on the first base substrate have areas that do not overlap with each other.

2. The display substrate of claim 1 , wherein the orthographic projections of the plurality of second signal lines on the first base substrate are within the orthographic projections of the plurality of first light-shielding structures on the first base substrate.

3. The display substrate of claim 1 , further comprising a plurality of second light-shielding structures arranged between the layers where the plurality of first signal lines and the plurality of second signal lines are located and the first base substrate;
wherein the plurality of second light-shielding structures extend along the first direction and are arranged along the second direction; and
the orthographic projections of the plurality of first signal lines on the first base substrate is within orthographic projections of the plurality of second light-shielding structures on the first base substrate.

4. The display substrate of claim 3 , wherein an orthographic projection of one first signal line on the first base substrate is on a side of an orthographic projection of a symmetry axis extending along the first direction of one second light-shielding structure;
on the same side of the symmetry axis extending along the first direction of the one second light-shielding structure, a distance by which the orthographic projection of the plurality of second light-shielding structures on the first base substrate extends outward relative to the orthographic projection of the plurality of first signal lines on the first base substrate is greater than 0 μm and less than or equal to 0.4 μm.

5. The display substrate of claim 3 , further comprising a plurality of transistors between the first base substrate and the layer where the plurality of pixel electrodes are located, and a planarization layer between the layer where the plurality of transistors are located and the layer where the plurality of pixel electrodes are located; wherein a first electrode of each transistor is electrically connected with each pixel electrode by means of a first through hole penetrating through the planarization layer;
an orthographic projection of the first through hole on the first base substrate is within the orthographic projections of the plurality of second light-shielding structures on the first base substrate.

6. The display substrate of claim 5 , wherein an orthographic projection of a symmetry axis extending along the first direction, of the plurality of second light-shielding structures on the first base substrate roughly coincides with an orthographic projection of a symmetry axis extending along the first direction, of the first through hole on the first base substrate.

7. The display substrate of claim 6 , wherein, on the same side of the symmetry axis extending along the first direction, of the plurality of second light-shielding structures, and in a direction where the plurality of second light-shielding structures is facing away from the first base substrate, an aperture of the first through hole gradually increases; and
the orthographic projection of the plurality of second light-shielding structures on the first base substrate extends outward by a distance greater than or equal to 0.8 μm and less than or equal to 1.0 μm relative to an orthographic projection of a maximum aperture of the first through hole on the first base substrate.

8. The display substrate of claim 5 , further comprising a gate insulating layer, a first interlayer dielectric layer and a second interlayer dielectric layer which are between the layer where the first electrode of each transistor is located and the layer where an active layer of each transistor is located;
wherein the first electrode of each transistor is electrically connected with the active layer of each transistor by means of a second through hole penetrating through the second interlayer dielectric layer, the first interlayer dielectric layer and the gate insulating layer; and
an orthographic projection of the second through hole on the first base substrate is within an orthographic projection of one second light-shielding structure on the first base substrate.

9. The display substrate of claim 8 , wherein the orthographic projection of the first signal line on the first base substrate and the orthographic projection of the second through hole on the first base substrate are respectively on both sides of the symmetry axis extending along the first direction, of the second light-shielding structure;
in a direction that the plurality of second light-shielding structures are facing away from the first base substrate, an aperture of the second through hole gradually increases;
in the second direction, a distance between the orthographic projection of the first signal line on the first base substrate and an orthographic projection of a maximum aperture of the second through hole on the first base substrate is approximately equal to a+√{square root over (2b 2 +c 2 )}, wherein a is a length of a light doping region of the active layer in each transistor in the second direction, b is ½ of a process fluctuation value of the first signal line and the second through hole, and c is an alignment deviation of the first signal line and the second through hole.

10. The display substrate of claim 9 , wherein on the same side of the symmetry axis extending along the first direction, of the second light-shielding structure, a distance by which the orthographic projection of the plurality of second light-shielding structures on the first base substrate extends outward relative to an orthographic projection of a maximum aperture of the second through hole is greater than or equal to 0.5 μm and less than 0.9 μm.

11. The display su

Assignees

• Ordos Yuansheng Optoelectronics Co Ltd
• Boe Technology Group Co Ltd

Inventors

• Yao Lei
• Li Feng
• Li Kai
• Su Haidong
• Wang Chenglong
• Hou Lin
• Xin Haoyi

Classifications

• H10W46/301

  for alignment · CPC title

• H10W46/00

  Marks applied to devices, e.g. for alignment or identification · CPC title

• G02F1/1368

  in which the switching element is a three-electrode device {(G02F1/136277 takes precedence)} · CPC title

• G02F1/136227

  Through-hole connection of the pixel electrode to the active element through an insulation layer · CPC title

• G02F1/136209

  Light shielding layers, e.g. black matrix, incorporated in the active matrix substrate, e.g. structurally associated with the switching element · CPC title