Method for III-v/silicon hybrid integration
US-11953728-B2 · Apr 9, 2024 · US
US12442993B2 · US · B2
| Field | Value |
|---|---|
| Publication number | US-12442993-B2 |
| Application number | US-202118257231-A |
| Country | US |
| Kind code | B2 |
| Filing date | Dec 17, 2021 |
| Priority date | Dec 18, 2020 |
| Publication date | Oct 14, 2025 |
| Grant date | Oct 14, 2025 |
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A system and method for alignment. In some embodiments, the method includes measuring a first offset, the first offset being an offset along a first direction between a first alignment mark and a second alignment mark, the first alignment mark being an alignment mark on a first edge of a source die, the second alignment mark being an alignment mark on a target wafer, and the first direction being substantially parallel to the first edge of the source die.
Opening claim text (preview).
What is claimed is: 1. A method, comprising: measuring a first offset, the first offset being an offset along a first direction between a first alignment mark and a second alignment mark, the first alignment mark being an alignment mark on a first edge of a source die, the second alignment mark being an alignment mark on a target wafer, the first direction being substantially parallel to the first edge of the source die, and measuring a second offset, the second offset being an offset along a second direction between a third alignment mark and a fourth alignment mark, wherein: the third alignment mark is an alignment mark on a second edge of the source die, the fourth alignment mark is an alignment mark on the target wafer, the second edge of the source die is substantially perpendicular to the first edge of the source die, the second direction is substantially parallel to the second edge of the source die, the second direction is substantially parallel to the target wafer, the fourth alignment mark is a first pillar on the target wafer, and the method further comprises measuring a third offset, along a third direction, between a top surface of the first pillar and an alignment feature of the source die. 2. The method of claim 1 , wherein: the target wafer is substantially planar, and the first direction is substantially parallel to the target wafer. 3. The method of claim 1 , wherein: the source die comprises a waveguide, on a top surface of the source die, the waveguide having a facet at a third edge of the source die, and the method further comprises forming, in one etching operation: the first alignment mark, and the facet. 4. The method of claim 3 , wherein the third edge is the same edge as the first edge. 5. The method of claim 1 , wherein: the target wafer comprises a waveguide, on a top surface of the target wafer, the waveguide having a sidewall, and the method further comprises forming, in one etching operation: the second alignment mark, and the sidewall. 6. The method of claim 1 , wherein: the third alignment mark is offset from the first pillar, on a first side of the first pillar, along the second direction, the source die comprises a fifth alignment mark, offset from the first pillar, on a second side of the first pillar, along the second direction, and the method comprises measuring one or more offsets, along the second direction, between the first pillar, the fourth alignment mark, and the fifth alignment mark. 7. The method of claim 1 , wherein the third direction is substantially perpendicular to the target wafer. 8. The method of claim 1 , wherein the alignment feature is an alignment plane. 9. The method of claim 1 , wherein a first portion of the first pillar is under the source die, and a second portion of the first pillar extends beyond the second edge of the source die. 10. The method of claim 1 , wherein: the target wafer comprises a waveguide having a facet, and the method further comprises forming, in one etching operation: the first pillar, and the facet of the waveguide of the target wafer. 11. The method of claim 1 , wherein the first edge of the source die comprises a plurality of alignment marks including the first alignment mark, and the target wafer comprises a plurality of corresponding alignment marks including the second alignment mark, each of the corresponding alignment marks corresponding to a respective one of the alignment marks of the first edge of the source die, the alignment marks of the first edge of the source die and the corresponding alignment marks forming a Vernier scale. 12. The method of claim 11 , wherein the plurality of corresponding alignment marks comprises five alignment marks. 13. The method of claim 1 , wherein: the target wafer comprises a second pillar, a first portion of the second pillar is under the source die, a second portion of the second pillar extends beyond a third edge of the source die, the third edge of the source die is substantially parallel to the first edge of the source die, and the method further comprises measuring a fourth offset, along a direction substantially perpendicular to the target wafer, between a top surface of the second pillar and an alignment feature of the source die. 14. The method of claim 1 , wherein: the top surface of the source die comprises a fiducial mark, the target wafer comprises a fiducial mark, and the method further comprises placing the source die on the target wafer at a position based on: the position of the fiducial mark on the source die; and the position of the fiducial mark on the top surface of the target wafer. 15. The method of claim 1 , wherein the measuring of the first offset comprises acquiring an image, the image including the first alignment mark and the second alignment mark.
Marks applied to devices, e.g. for alignment or identification · CPC title
for use after dicing · CPC title
for alignment · CPC title
characterised by the type of information, e.g. logos or symbols · CPC title
using visual alignment markings, e.g. index methods · CPC title
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