Hybrid integration for photonic integrated circuits

Patent metadata

Field	Value
Publication number	US-11340400-B2
Application number	US-202016809640-A
Country	US
Kind code	B2
Filing date	Mar 5, 2020
Priority date	Mar 6, 2019
Publication date	May 24, 2022
Grant date	May 24, 2022

Abstract

Photonic integrated circuits (PICs) enable manipulation of light on a chip for telecommunications and information processing. They can be made with silicon and silicon-compatible materials using complementary metal-oxide-semiconductor (CMOS) fabrication techniques developed for making electronics. Unfortunately, most light sources are made with III-V and II-VI materials, which are not compatible with silicon CMOS fabrication techniques. As a result, the light source for a PIC is either off-chip or integrated onto the PIC after CMOS fabrication is over. Hybrid integration can be improved by forming a recess in the PIC to receive a III-V or II-VI photonic chip. Mechanical stops formed in or next to the recess during fabrication align the photonic chip vertically to the PIC. Fiducials on the PIC and the photonic chip enable sub-micron lateral alignment. As a result, the photonic chip can be flip-chip bonded to the PIC with sub-micron vertical and lateral alignment precision.

First claim

The invention claimed is:

1. A method of integrating a photonic chip with a photonic integrated circuit (PIC), the method comprising:
forming a bottom cladding having a thickness of at least 3 μm on a substrate of the PIC;
forming a waveguide core on the bottom cladding;
exposing a surface of the substrate next to the waveguide core;
forming dielectric layer on the surface of substrate next to the waveguide core and on the waveguide core, the dielectric layer on the waveguide core forming a top cladding;
patterning at least a portion of the dielectric layer on the surface of substrate next to the waveguide core to form a dielectric pedestal next to a recess; and
placing the photonic chip on the dielectric pedestal to align the photonic chip with the waveguide core.

2. The method of claim 1 , wherein the photonic chip comprises at least one of a III-V or II-VI material.

3. The method of claim 1 , wherein the photonic chip is a Slab Coupled Optical Waveguide Amplifier (SCOWA) with a transverse mode diameter of at least than 3 μm.

4. The method of claim 1 , wherein placing the photonic chip on the dielectric pedestal comprises aligning the waveguide core to within 0.5 μm of a waveguide in the photonic chip.

5. The method of claim 1 , wherein placing the photonic chip on the dielectric pedestal comprises electrically connecting the photonic chip to the silicon PIC.

6. The method of claim 5 , further comprising:
forming an electrical connection between the photonic chip and a back side of the substrate through a through-silicon via (TSV).

7. The method of claim 1 , further comprising:
annealing the dielectric layer before patterning the at least a portion of the dielectric layer to form the dielectric pedestal.

8. The method of claim 1 , wherein the dielectric layer is a first dielectric layer, and further comprising, before placing the photonic chip on the dielectric pedestal:
depositing a second dielectric layer over at least portion of the recess;
depositing pad metal on at least a portion of the second dielectric layer;
patterning a solder bump on the pad metal; and
bonding the photonic chip to the pad metal with the solder bump.

9. The method of claim 1 , further comprising:
forming an electrode in the PIC; and
electrically connecting the photonic chip to the electrode.

10. The method of claim 9 , wherein forming the electrode comprises:
depositing and patterning a first metal layer in the recess;
depositing dielectric material over at least a portion of the first metal layer; and
depositing a second metal layer in electrical communication with the first metal layer.

11. The method of claim 1 , further comprising:
forming a plurality of lateral alignment marks on the PIC for laterally aligning the photonic chip to the PIC.

12. The method of claim 1 , wherein the waveguide core is part of a first waveguide array formed in the PIC, and wherein placing the photonic chip on the dielectric pedestal comprises aligning the first waveguide array to a second waveguide array formed in the photonic chip.

13. A method of integrating a photonic chip with a photonic integrated circuit (PIC), the method comprising:
forming a waveguide in the PIC;
forming a recess in the PIC, the waveguide terminating at a facet forming one side of the recess;
forming a dielectric pedestal in the recess; and
disposing the photonic chip on the dielectric pedestal such that a waveguide in the photonic chip is vertically and laterally aligned to the waveguide terminating at the facet.

14. The method of claim 13 , further comprising:
bonding the photonic chip to conductive material on a bottom surface of the recess.

15. The method of claim 14 , further comprising, bonding the photonic chip to the conductive material:
patterning the conductive material to form an electrode.

16. A method of integrating a III-V photonic chip with a photonic integrated circuit (PIC) formed in a silicon substrate, the method comprising:
depositing a first silicon oxide layer on the silicon substrate, the first silicon oxide layer forming a bottom cladding of a PIC waveguide;
depositing silicon nitride on a first portion of the first silicon oxide layer;
patterning the silicon nitride to form a core of the PIC waveguide;
etching a second portion of the first silicon oxide layer to expose a portion of the silicon substrate;
depositing a second silicon oxide layer over the portion of the silicon substrate and the core of the PIC waveguide, the second silicon oxide layer over the core of the PIC waveguide forming a top cladding of the PIC waveguide;
etching a trench through the first silicon oxide layer and/or the second silicon oxide layer, the trench defining a coupling facet of the PIC waveguide and a mechanical stop;
depositing a third silicon oxide layer within at least a portion of the trench;
depositing pad metal on a portion of third silicon oxide layer;
forming a solder bump on the pad metal; and
bonding the III-V photonic chip to the pad metal with the solder bump, the mechanical stop aligning a photonic chip waveguide in the III-V photonic chip to the coupling facet of the PIC waveguide.

17. The method of claim 16 , further comprising, before etching the trench:
annealing the first silicon oxide layer and/or the second silicon oxide layer.

18. The method of claim 16 , further comprising, before forming the solder bump on the pad metal:
forming an electrical connection between the pad metal and a metal layer on the silicon substrate.

19. The method of claim 16 , further comprising, before bonding the III-V photonic chip to the pad metal with the solder bump:
patterning the pad metal to form an electrode.

20. The method of claim 16 , further comprising, before bonding the III-V photonic chip to the pad metal with the solder bump:
forming lateral alignment marks on the PIC; and
aligning the lateral alignment marks on the PIC to lateral alignment marks on the III-V photonic chip.

Assignees

• Massachusetts Inst Technology

Inventors

• Kharas Boris
• Swint Reuel B
• Sorace-Agaskar Cheryl Marie
• Juodawlkis Paul William
• Bramhavar Suraj Deepak
• Plant Jason

Classifications

• H10F77/40

  Optical elements or arrangements (surface textures H10F77/70) · CPC title

• H10F55/00

  Radiation-sensitive semiconductor devices covered by groups H10F10/00, H10F19/00 or H10F30/00 being structurally associated with electric light sources and electrically or optically coupled thereto · CPC title

• G02B6/12004 Primary

  Combinations of two or more optical elements · CPC title

• G02B6/4228

  Passive alignment, i.e. without a detection of the degree of coupling or the position of the elements (G02B6/4234 takes precedence) · CPC title

• G02B2006/12061

  Silicon · CPC title