Semiconductor device and method for fabricating the same

Patent metadata

Field	Value
Publication number	US-12439681-B2
Application number	US-202418613151-A
Country	US
Kind code	B2
Filing date	Mar 22, 2024
Priority date	Dec 4, 2017
Publication date	Oct 7, 2025
Grant date	Oct 7, 2025

Abstract

A semiconductor device includes a fin-shaped structure on a substrate, a gate structure on the fin-shaped structure and an interlayer dielectric (ILD) layer around the gate structure, and a single diffusion break (SDB) structure in the ILD layer and the fin-shaped structure. Preferably, the SDB structure includes a bottom portion and a top portion on the bottom portion, in which the top portion and the bottom portion include different widths.

First claim

What is claimed is:

1. A semiconductor device, comprising:
a fin-shaped structure on a substrate;
a gate structure on the fin-shaped structure and an interlayer dielectric (ILD) layer around the gate structure;
an epitaxial layer adjacent to the gate structure;
a single diffusion break (SDB) structure in the ILD layer and the fin-shaped structure, wherein the SDB structure comprises:
a bottom portion comprising a first width and a second width, wherein a top surface of the bottom portion is higher than a top surface of the epitaxial layer; and
a top portion on the bottom portion, wherein the top portion comprise a third width and a top surface of the bottom portion is higher than a top surface of the fin-shaped structure.

2. The semiconductor device of claim 1 , further comprising:
a first spacer around the gate structure;
a second spacer around the SDB structure; and
a contact etch stop layer (CESL) between the first spacer and the second spacer.

3. The semiconductor device of claim 2 , wherein the first spacer and the second spacer comprise different heights.

4. The semiconductor device of claim 2 , wherein the CESL is U-shaped.

5. The semiconductor device of claim 2 , wherein a top surface of the CESL adjacent to the second spacer is lower than a top surface of the CESL adjacent to the first spacer.

6. The semiconductor device of claim 1 , wherein a top surface of the bottom portion is even with a top surface of the gate structure.

7. The semiconductor device of claim 1 , wherein the SDB structure comprises:
a liner; and
a dielectric layer on the liner, wherein the liner and the dielectric layer comprise different material.

8. The semiconductor device of claim 1 , further comprising an air gap in the SDB structure.

9. The semiconductor device of claim 1 , wherein the fin-shaped structure is disposed extending along a first direction and the SDB structure is disposed extending along a second direction.

10. The semiconductor device of claim 9 , wherein the first direction is orthogonal to the second direction.

Assignees

• United Microelectronics Corp

Inventors

• Lin Ching-Ling
• Liang Wen-An
• Huang Chen-Ming

Classifications

• H10W10/021 Primary

  of air gaps · CPC title

• H10W10/20

  Air gaps · CPC title

• H10W10/17

  formed using trench refilling with dielectric materials, e.g. shallow trench isolations · CPC title

• H10W10/014

  using trench refilling with dielectric materials, e.g. shallow trench isolations · CPC title

• H10D84/834

  comprising FinFETs · CPC title