Method and structure for FinFET isolation

Patent metadata

Field	Value
Publication number	US-9490176-B2
Application number	US-201414579728-A
Country	US
Kind code	B2
Filing date	Dec 22, 2014
Priority date	Oct 17, 2014
Publication date	Nov 8, 2016
Grant date	Nov 8, 2016

Abstract

A semiconductor device with effective FinFET isolation and method of forming the same are disclosed. The method includes receiving a substrate having an active fin, a plurality of dummy gate stacks over the substrate and engaging the fin, and first dielectric features over the substrate and separating the dummy gate stacks. The method further includes removing the dummy gate stacks thereby forming a first trench and a second trench that expose first and second portions of the active fin respectively. The method further includes removing the first portion of the active fin and forming a gate stack in the second trench, the gate stack engaging the second portion of the active fin. The method further includes filling the first trench with a second dielectric material that effectively isolates the second portion of the active fin.

First claim

What is claimed is:

1. A method of forming a semiconductor device, comprising:
receiving a substrate having an active fin, a plurality of dummy gate stacks over the substrate and engaging the fin, and first dielectric features over the substrate and between the dummy gate stacks;
removing the dummy gate stacks thereby forming a first trench and a second trench, wherein the first and second trenches expose first and second portions of the active fin respectively;
removing the first portion of the active fin; and
forming a gate stack in the second trench, the gate stack engaging the second portion of the active fin.

2. The method of claim 1 , wherein the dummy gate stacks and the first dielectric features are separated by spacer features.

3. The method of claim 1 , further comprising:
filling the first trench with a second dielectric material.

4. The method of claim 1 , wherein the dummy gate stacks are over a first surface of an isolation structure over the substrate, and the removing of the first portion of the active fin includes:
expanding the first trench below the first surface.

5. The method of claim 1 , wherein the removing of the first portion of the active fin includes:
forming a masking element over the second portion of the active fin; and
performing an etching process to the first portion of the active fin.

6. The method of claim 1 , further comprising, after the removing of the first portion of the active fin:
performing an ashing process to the first trench so as to recess the active fin along its length.

7. The method of claim 6 , wherein:
the dummy gate stacks and the first dielectric features are separated by spacer features having a first thickness; and
the ashing process recesses the active fin by a distance less than the first thickness.

8. The method of claim 6 , wherein the ashing process exposes a first surface of the active fin, further comprising:
forming a second dielectric layer over the first surface.

9. The method of claim 8 , wherein the second dielectric layer includes one of: silicon oxide and silicon nitride.

10. The method of claim 1 , wherein the gate stack includes a high-k dielectric layer and a work function metal layer.

11. A method of forming a semiconductor device, comprising:
receiving a substrate having an active fin, an isolation structure over the substrate, a plurality of dummy gate stacks over a first surface of the isolation structure and engaging the fin, spacer features over the first surface and on sidewalls of the dummy gate stacks, and first dielectric features over the first surface and between the spacer features;
removing the dummy gate stacks thereby forming first, second, and third trenches, wherein the second trench is between the first and third trenches, and the first, second, and third trenches expose first, second, and third portions of the active fin respectively;
removing the second portion of the active fin; and
forming gate stacks in the first and third trenches, the gate stacks engaging the first and third portions of the active fin.

12. The method of claim 11 , wherein the removing of the second portion of the active fin includes:
forming a masking element covering the first and third portions of the active fin; and
etching the second portion of the active fin below the first surface.

13. The method of claim 12 , further comprising:
performing an ashing process to both remove the masking element and to recess the active fin through the second trench.

14. The method of claim 11 , further comprising, after the removing of the second portion of the active fin:
performing one of oxidation and nitridation processes to surfaces of the active fin that are exposed through the second trench.

15. The method of claim 11 , further comprising:
filling the second trench with a second dielectric material.

16. A method of forming a semiconductor device, comprising:
receiving a substrate having first and second active fins, wherein each of the first and second active fins has first and second ends, and the second end of the first active fin is adjacent to the first end of the second active fin;
forming a first gate stack over the substrate and engaging the first active fin;
forming a second gate stack over the substrate and engaging the second active fin;
forming a first isolation structure over the first end of the first active fin from a top view;
forming a second isolation structure over the second end of the second active fin from the top view; and
forming a third isolation structure adjacent to both the second end of the first active fin and the first end of the second active fin from the top view.

17. The method of claim 16 , wherein each of the first, second, and third isolation structures is surrounded by respective spacer features.

18. The method of claim 16 , further comprising:
forming a fourth isolation structure over the substrate, wherein the first and second gate stacks are formed over the fourth isolation structure.

19. The method of claim 18 , wherein:
the first and second gate stacks are formed over a first surface of the fourth isolation structure; and

the third isolation structure is formed over a second surface of the fourth isolation structure, wherein the second surface is lower than the first surface from a cross sectional view.

20. The method of claim 16 , wherein the second end of the first active fin and the first end of the second active fin each include a dielectric material layer abutting the third isolation structure, and the dielectric material layer is one of: silicon oxide and silicon nitride.

Assignees

• Taiwan Semiconductor Mfg Co Ltd

Inventors

• Chang Che-Cheng
• Lin Chih-Han
• Lin Jr-Jung

Classifications

• H10D30/792

  comprising applied insulating layers, e.g. stress liners · CPC title

• H10D30/611

  having multiple independently-addressable gate electrodes influencing the same channel (FinFETs having multiple distinct gate electrodes H10D30/6215; multi-gate TFT H10D30/6733) · CPC title

• H10D30/6215 Primary

  having multiple independently-addressable gate electrodes · CPC title

• H10D84/834

  comprising FinFETs · CPC title

• H10D84/0158

  the components including FinFETs · CPC title