Semiconductor device structure with gate spacer having protruding bottom portion and method for forming the same

Patent metadata

Field	Value
Publication number	US-9502412-B2
Application number	US-201414490888-A
Country	US
Kind code	B2
Filing date	Sep 19, 2014
Priority date	Sep 19, 2014
Publication date	Nov 22, 2016
Grant date	Nov 22, 2016

Abstract

A semiconductor device structure and method for forming the same are provided. The semiconductor device structure includes a substrate and a gate stack structure formed on the substrate. The semiconductor device structure also includes gate spacers formed on the sidewall of the gate stack structure, and the gate spacers include a top portion and a bottom portion adjoined to the top portion, and the bottom portion slopes to a top surface of the substrate. The semiconductor device structure further includes an epitaxial structure formed adjacent to the gate spacers, and the epitaxial structure is formed below the gate spacers.

First claim

What is claimed is:

1. A semiconductor device structure, comprising:
a substrate;
a gate stack structure formed on the substrate, wherein the gate stack structure comprises a gate dielectric layer and a gate electrode layer over the gate dielectric layer;
gate spacers formed on the sidewalls of the gate stack structure, wherein the gate spacers comprise a top portion and a protruding bottom portion directly below the top portion, the top portion and the protruding bottom portion form a recessed corner at a joint of the top portion and the protruding bottom portion, the recessed corner is lower than a top of the gate dielectric, and the protruding bottom portion slopes to a top surface of the substrate; and
an epitaxial structure formed adjacent to the gate spacers, wherein the epitaxial structure is formed below the gate spacers.

2. The semiconductor device structure as claimed in claim 1 , wherein the top portion of the gate spacers has a first outer surface, the protruding bottom portion of the gate spacers has a second outer surface, an angle between the first outer surface and the second outer surface is in a range from about 90 degrees to about 178 degrees.

3. The semiconductor device structure as claimed in claim 1 , wherein the top portion has a uniform thickness.

4. The semiconductor device structure as claimed in claim 1 , wherein the protruding bottom portion of the gate spacers has a bottom surface which is in direct contact with the substrate, and the bottom surface has a maximum thickness.

5. The semiconductor device structure as claimed in claim 4 , wherein the maximum thickness is in a range from about 5 nm to about 12 nm.

6. The semiconductor device structure as claimed in claim 1 , wherein the epitaxial structure comprises a silicon germanium (SiGe) structure.

7. The semiconductor device structure as claimed in claim 1 , wherein the epitaxial structure has a raised height which is above a top surface of the substrate in a range from about 12 nm to about 21 nm.

8. The semiconductor device structure as claimed in claim 1 , wherein the protruding bottom portion of the gate spacers is gradually increased towards the substrate.

9. A semiconductor device structure, comprising:
a substrate;
a first gate stack structure and a second gate stack structure formed on the substrate, wherein the first gate stack structure comprises a first gate dielectric layer and a first gate electrode layer over the first gate dielectric layer;
first gate spacers formed on the sidewalls of the first gate stack structure, wherein the first gate spacers comprise a top portion and a protruding bottom portion directly below the top portion, the top portion and the protruding bottom portion form a recessed corner at a joint of the top portion and the protruding bottom portion, and the recessed corner is lower than a top of the gate dielectric;
second gate spacers formed on the sidewalls of the second gate stack structure;
a first epitaxial structure formed adjacent to the first gate stack structure, wherein the protruding bottom portion is in direct contact with the first epitaxial structure; and
a second epitaxial structure formed adjacent to the second gate stack structure.

10. The semiconductor device structure as claimed in claim 9 , wherein the first gate stack structure is a PMOS gate stack structure, and the second gate stack structure is a NMOS gate stack structure.

11. The semiconductor device structure as claimed in claim 9 , wherein the first epitaxial structure is silicon germanium (SiGe), and the second epitaxial structure is silicon phosphate (SiP).

12. The semiconductor device structure as claimed in claim 9 , wherein the top portion of the first gate spacers has a first outer surface, the protruding bottom portion of the gate spacers has a second outer surface, an angle between the first outer surface and the second outer surface is in a range from about 90 degrees to about 178 degrees.

13. The semiconductor device structure as claimed in claim 9 , wherein the second gate spacers have a uniform thickness.

14. The semiconductor device structure as claimed in claim 9 , wherein the protruding bottom portion of the first gate spacers is gradually increased towards the substrate.

15. The semiconductor device structure as claimed in claim 9 , wherein the protruding bottom portion of the first gate spacers has a bottom surface which is in direct contact with the substrate, and the bottom surface has a maximum thickness.

16. The semiconductor device structure as claimed in claim 9 , wherein the first epitaxial structure has a raised height which is above a top surface of the substrate in a range from about 12 nm to about 21 nm.

17. A semiconductor device structure, comprising:
a substrate;
a first gate stack structure and a second gate stack structure formed on the substrate, wherein the first gate stack structure comprises a first gate dielectric layer and a first gate electrode layer over the first gate dielectric layer;
first gate spacers formed on the sidewalls of the first gate stack structure, wherein the first gate spacers comprise a top portion and a protruding bottom portion directly below the top portion, the top portion and the protruding bottom portion form a recessed corner at a joint of the top portion and the protruding bottom portion, and the recessed corner is lower than a top of the gate dielectric;
a first epitaxial structure formed adjacent to the first gate stack structure, wherein the protruding bottom portion of the first gate spacer is gradually increased towards the substrate, and the first epitaxial structure is silicon germanium (SiGe); and
a second epitaxial structure formed adjacent to the second gate stack structure, wherein the second epitaxial structure is silicon phosphate (SiP).

18. The semiconductor device structure as claimed in claim 17 , wherein the protruding bottom portion is in direct contact with the first epitaxial structure.

19. The semiconductor device structure as claimed in claim 17 , wherein the protruding bottom portion of the first gate spacers has a bottom surface which is in direct contact with the substrate, and the bottom surface has a maximum thickness.

20. The semiconductor device structure as claimed in claim 17 , further comprising:
second gate spacers formed on the sidewalls of the second gate stack structure, wherein a profile of the second spacers is different from the profile of the first spacers.

Assignees

• Taiwan Semiconductor Mfg Co Ltd

Inventors

• Liu Yung-Tsun

Classifications

• H10P95/70

  Chemical treatments · CPC title

• H10P52/00

  Grinding, lapping or polishing of wafers, substrates or parts of devices · CPC title

• H10P50/283

  by chemical means · CPC title

• H10P50/20

  Dry etching; Plasma etching; Reactive-ion etching · CPC title

• H10D64/011

  of electrodes ohmically coupled to a semiconductor · CPC title