Isolation structures

Patent metadata

Field	Value
Publication number	US-12439678-B2
Application number	US-202117402079-A
Country	US
Kind code	B2
Filing date	Aug 13, 2021
Priority date	Aug 13, 2021
Publication date	Oct 7, 2025
Grant date	Oct 7, 2025

Abstract

Semiconductor structures and methods are provided. An exemplary method according to the present disclosure includes receiving a fin-shaped structure comprising a first channel region and a second channel region, a first and a second dummy gate structures disposed over the first and the second channel regions, respectively. The method also includes removing a portion of the first dummy gate structure, a portion of the first channel region and a portion of the substrate under the first dummy gate structure to form a trench, forming a hybrid dielectric feature in the trench, removing a portion of the hybrid dielectric feature to form an air gap, sealing the air gap, and replacing the second dummy gate structure with a gate stack after sealing the air gap.

First claim

What is claimed is:

1. A method, comprising:
receiving a workpiece comprising:
a fin-shaped structure protruding from a substrate and comprising a first channel region and a second channel region,
a first dummy gate structure disposed over the first channel region and a second dummy gate structure disposed over the second channel region, and
a source/drain feature disposed between the first channel region and the second channel region;

removing a portion of the first dummy gate structure to form a first trench exposing the first channel region;
removing a portion of the first channel region exposed by the first trench and a portion of the substrate directly under the first channel region to extend the first trench;
forming a dielectric feature in the extended first trench, wherein the dielectric feature is spaced apart from the source/drain feature by an air gap; and
after the forming of the dielectric feature, replacing the second dummy gate structure with a gate stack.

2. The method of claim 1 , wherein the forming of the dielectric feature comprises:
forming a dummy liner over a sidewall surface the extended first trench;
forming a dielectric filler over the dummy liner to fill the extended first trench; and
selectively removing the dummy liner to form a second trench and release the dielectric filler as the dielectric feature.

3. The method of claim 2 , wherein a dielectric constant of dummy liner is greater than a dielectric constant of the dielectric filler.

4. The method of claim 2 ,
wherein the dummy liner comprises silicon nitride, silicon oxycarbonitride, silicon carbonitride, or silicon oxynitride, and
wherein the dielectric filler comprises silicon oxide.

5. The method of claim 2 , further comprising:
forming a seal material layer over the workpiece, the seal material layer comprising a first portion plugging the second trench,
wherein a bottom surface of the first portion of the seal material layer is lower than a top surface of the source/drain feature.

6. The method of claim 5 , wherein the replacing of the second dummy gate structure with the gate stack comprises:
after forming the seal material layer, removing the second dummy gate structure without substantially etching the seal material layer; and
forming the gate stack over the second channel region.

7. The method of claim 6 , wherein the dielectric feature is spaced apart from a rest of the first channel region by the second trench.

8. The method of claim 6 ,
wherein the seal material layer further comprises a second portion disposed on a bottom surface of the extended first trench.

9. The method of claim 2 , wherein the forming of the dielectric feature further comprises:
after the forming of the dummy liner, depositing a dummy layer over the dummy liner to fill a bottom portion of the extended first trench,
wherein the dielectric filler is deposited on the dummy layer to fill an upper portion of the extended first trench,
wherein the selectively removing of the dummy liner further removes the dummy layer without substantially removing the dielectric filler.

10. A method, comprising:
receiving a workpiece comprising:
a first active region and a second active region extending from a substrate,
a first isolation feature disposed over the substrate and between the first and the second active regions,
a second isolation feature disposed on the first isolation feature, and
a dummy gate structure comprising a first portion over the first active region and a second portion over the second active region;

removing the first portion of the dummy gate structure and portions of the first active region and the substrate under the first portion of the dummy gate structure to form a trench;
forming a dielectric feature in the trench, wherein the dielectric feature is spaced apart from the second isolation feature by an air gap; and
replacing the second portion of the dummy gate structure with a gate stack.

11. The method of claim 10 ,
wherein the first active region and the second active region each include a vertical stack of alternating sacrificial layers and channel layers over the substrate,
wherein the workpiece further comprises a cladding layer extending along sidewalls of the first active region and the second active region, and
wherein the dielectric feature is spaced apart from the cladding layer by the air gap.

12. The method of claim 10 , wherein the forming of the dielectric feature comprises:
forming a sacrificial liner over a sidewall surface and a bottom surface of the trench;
forming a dielectric filler over the sacrificial liner to fill the trench; and
selectively removing the sacrificial liner to form a gap and release the dielectric filler as the dielectric feature.

13. The method of claim 12 , further comprising:
forming a seal material layer over the workpiece to seal the gap, thereby forming the air gap.

14. The method of claim 13 , wherein a bottom surface of the seal material layer is in direct contact with a top surface of the second isolation feature.

15. The method of claim 13 ,
wherein the dielectric filler is spaced apart from the second portion of the dummy gate structure by the seal material layer, and
wherein the replacing of the second portion of the dummy gate structure with the gate stack comprises removing the second portion of the dummy gate structure without substantially removing the seal material layer.

16. The method of claim 12 , wherein the sacrificial liner comprises a high-k material and the dielectric filler comprises a low-k material.

17. A method, comprising:
receiving a semiconductor structure comprising:
a channel region directly over a portion of a substrate,
a dummy gate structure directly over the channel region, and
a source/drain feature over the substrate and electrically coupled to the channel region;

removing the dummy gate structure, the channel region, and the portion of the substrate disposed directly under the channel region to form a trench;
forming a dielectric feature in the trench, wherein the dielectric feature is spaced apart from the source/drain feature and the substrate by an air gap, wherein the air gap extends into the substrate.

18. The method of claim 17 , wherein the forming of the dielectric feature comprises:
conformal depositing a first dielectric layer, the first dielectric layer partially fills the trench;
forming a second dielectric layer over the first dielectric layer; and
selectively removing the first dielectric layer to form the air gap.

19. The method of claim 17 , wherein the channel region comprises a vertical stack of alternating channel layers and sacrificial layers.

20. The method of claim 17 ,
wherein the dummy gate structure comprises a dummy gate dielectric layer and a dummy gate electrode disposed over the dummy gate dielectric layer, and
wherein the removing of the dummy gate structure, the channel region, and the portion of the substrate disposed directly under the channel region to form the trench comprises:
performing a first etching process to selectively etch the dummy gate electrode to form a first trench; and
performing a second etching process to vertically extend the first trench by removing a portion of the dummy gate dielectric layer exposed by the first trench and removing the channel region and the portion of the substrate disposed directly under the portion of the dummy gate dielectric layer.

Assignees

• Taiwan Semiconductor Mfg Co Ltd

Inventors

• LEE Kai-Hsuan
• Lin Shih-Che
• Huang Po-Yu
• Wu Shih-Chieh
• Wu I-Wen
• Lee Chen-Ming
• Yang Fu-Kai
• Wang Mei-Yun

Classifications

• H10P14/3452

  Microstructure · CPC title

• H10W10/021

  of air gaps · CPC title

• H10W10/20

  Air gaps · CPC title

• H10D84/0167

  Manufacturing their channels · CPC title

• H10D84/85

  Complementary IGFETs, e.g. CMOS · CPC title