Stacked field effect transistors with reduced coupling effect

Patent metadata

Field	Value
Publication number	US-11069684-B1
Application number	US-202016809205-A
Country	US
Kind code	B1
Filing date	Mar 4, 2020
Priority date	Mar 4, 2020
Publication date	Jul 20, 2021
Grant date	Jul 20, 2021

Abstract

A semiconductor structure includes a first field-effect transistor disposed on a substrate. The first field-effect transistor includes a first metal gate, and a first source/drain region. A second field-effect transistor is vertically stacked above the first field-effect transistor. The second field-effect transistor includes a second metal gate, and a second source/drain region. The first metal gate and the second metal gate are vertically aligned and configured with an air gap disposed therebetween. The first source/drain region and the second source/drain region are vertically aligned and configured with another air gap disposed therebetween.

First claim

What is claimed is:

1. A method for forming a semiconductor structure, comprising:
forming a first set of nanosheet layers and a second set of nanosheet layers on a substrate, wherein each of the first set of nanosheet layers and the second set of nanosheet layers comprises alternating silicon layers and silicon-germanium layers, and wherein the first set of nanosheet layers and the second set of nanosheet layers are separated by a first sacrificial isolation layer;
forming a bottom source/drain region on the substrate and in contact with the first set of nanosheet layers;
forming a second sacrificial isolation layer on at least the bottom source/drain region;
forming a top source/drain region on at least a portion of the second sacrificial isolation layer;
depositing an interlevel dielectric layer on the top source/drain region and the second sacrificial isolation layer;
forming one or more trenches in the interlevel dielectric layer and exposing a top surface of the second sacrificial isolation layer; and
removing the second sacrificial isolation layer to form an air gap positioned between the bottom source/drain region and the top source/drain region.

2. The method of claim 1 , further comprising:
forming a first metal contact to provide electrical contact with the bottom source/drain region; and
forming a second metal contact to provide electrical contact with the top source/drain region.

3. The method of claim 1 , wherein a bottom-most nanosheet layer and a top-most nanosheet layer of the first set of nanosheet layers are silicon-germanium layers and further wherein the bottom-most nanosheet layer of the second set of nanosheet layers is a silicon-germanium layer and the top-most nanosheet layer of the second set of nanosheet layers is a silicon layer.

4. The method of claim 1 , wherein the first set of nanosheet layers and the second set of nanosheet layers each comprise a divot in respective silicon-germanium layers, wherein an inner spacer is formed within the divot.

5. The method of claim 1 , wherein forming the first set of nanosheet layers and the second set of nanosheet layers comprises:
epitaxially growing the first set of nanosheet layers, wherein a bottom-most layer of the first set of nanosheet layers is a first silicon-germanium layer and a top-most layer of the first nanosheet layers is a second silicon-germanium;
forming a third silicon-germanium layer on the top-most second silicon-germanium layer of the first set of nanosheet layers, wherein the third silicon-germanium layer is different than the first silicon-germanium layer and the second silicon-germanium layer;
epitaxially growing the second set of nanosheet layers on the third silicon-germanium layer, wherein a bottom-most layer of the second set of nanosheet layers is a first silicon-germanium layer and a top-most layer of the second set of nanosheet layers is a silicon layer, wherein the third silicon-germanium layer is different than the first silicon-germanium layer;
forming a plurality of dummy gates on a portion of the top-most layer of the second nanosheet stack, the plurality of dummy gates being protected by a hardmask on a top surface thereof;
forming gate spacers on sidewalls of each of the plurality of dummy gates and sidewalls of the hardmask;
replacing the third silicon-germanium layer with the first sacrificial isolation layer; and
etching the first set of nanosheet layers, the first sacrificial isolation layer and the second set of nanosheet layers such that portions of the first set of nanosheet layers, the first sacrificial isolation layer and the second set of nanosheet layers not underneath the gate spacers and the plurality of dummy gates are removed.

6. The method of claim 5 , further comprising:
selectively etching a portion of the silicon-germanium layers of the first set of nanosheet layers and the second set of nanosheet layers; and
forming inner spacers in the etched portions of the silicon-germanium layers.

7. The method of claim 6 , further comprising:
removing the hardmask, the plurality of dummy gates and the silicon-germanium layers of the first set of nanosheet layers and the second set of nanosheet layers;
forming a replacement metal gate in place of the removed dummy gate and removed silicon-germanium layers of the first set of nanosheet layers and the second set of nanosheet layers; and
forming a cap over a top surface of the replacement metal gate.

8. The method of claim 7 , wherein the replacement metal gate is a high-k metal gate.

9. The method of claim 7 , further comprising:
forming a first metal contact to provide electrical contact with the bottom source/drain region;
forming a second metal contact to provide electrical contact with the top source/drain region; and
forming a third metal contact to provide electrical contact with the replacement metal gate.

10. The method of claim 7 , further comprising removing the first sacrificial isolation layer to form another air gap positioned between a top-most replacement metal gate of the first set of nanosheet layers and a bottom-most replacement metal gate of the second set of nanosheet layers.

11. The method of claim 1 , further comprising depositing a dielectric layer in at least a top portion of the one or more trenches, wherein the dielectric layer seals the air gap positioned between the bottom source/drain region and the top source/drain region.

12. A method of forming a stacked integrated circuit structure, comprising:
forming a plurality of stacked field-effect transistors comprising a first field-effect transistor and a second field-effect transistor on a substrate, wherein the first field-effect transistor and the second field-effect transistor are separated by a first sacrificial isolation layer, wherein the first field-effect transistor comprises a first metal gate and a first source/drain region, wherein the second field-effect transistor comprises a second metal gate, and a second source/drain region, wherein the first metal gate and the second metal gate are vertically aligned, and wherein the first source/drain region and the second source/drain region are vertically aligned and separated by a second sacrificial isolation layer;
forming an interlevel dielectric layer over the second source/drain region and on the second sacrificial isolation layer;
forming one or more trenches in the interlevel dielectric layer and exposing a top surface of the second sacrificial isolation layer; and
removing the second sacrificial isolation layer to form an air gap positioned between the first source/drain region and the second source/drain region.

13. The method of claim 12 , further comprising:
forming a first metal contact to provide electrical contact with the first source/drain region; and
forming a second metal contact to provide electrical contact with the second source/drain region.

14. The method of claim 12 , wherein forming the plurality of stacked field-effect transistors comprises:
epitaxially growing a first set of nanosheet layers comprising alternating layers of silicon-germanium and silicon, wherein a bottom-most layer of the first set of nanosheet layers is a silicon-germanium bottom layer and a top-most layer of the first nanosheet layers is a silicon-germanium top layer;
forming a silicon-germanium isolation layer on the silicon-germanium top layer of the first set of nanosheet layers, wherein the silicon-germanium isolation layer is different than the silicon-germanium bottom layer and the second silicon-germanium top layer;
epitaxially growing a second set of nanosheet layers comprising alternating layers of sili

Assignees

• IBM

Inventors

• Xie Ruilong
• Yeh Chun-Chen
• Guo Dechao
• Reznicek Alexander

Classifications

• H10P50/242

  of Group IV materials · CPC title

• H10P14/3462

  Nanowires · CPC title

• H10P14/3411

  Silicon, silicon germanium or germanium · CPC title

• H10W10/021

  of air gaps · CPC title

• H10W10/20

  Air gaps · CPC title