Co-deposition of titanium and silicon for improved silicon germanium source and drain contacts

Patent metadata

Field	Value
Publication number	US-12439669-B2
Application number	US-202117358436-A
Country	US
Kind code	B2
Filing date	Jun 25, 2021
Priority date	Jun 25, 2021
Publication date	Oct 7, 2025
Grant date	Oct 7, 2025

Abstract

Source and drain contacts that provide improved contact resistance and contact interface stability for transistors employing silicon and germanium source and drain materials, related transistor structures, integrated circuits, systems, and methods of fabrication are disclosed. Such source and drain contacts include a contact layer of co-deposited titanium and silicon on the silicon and germanium source and drain. The disclosed source and drain contacts improve transistor performance including switching speed and reliability.

First claim

What is claimed is:

1. An apparatus, comprising:
a channel region between a source and a drain, the source and the drain each comprising silicon and germanium;
a gate electrode adjacent to the channel region; and
a contact comprising a contact layer on at least one of the source or the drain, the contact layer comprising titanium, silicon, and germanium comprising a germanium concentration of not more than 5% at any position through a thickness of the contact layer.

2. The apparatus of claim 1 , wherein the germanium concentration of the contact layer is not more than 2.5% at any position through the thickness of the contact layer.

3. The apparatus of claim 1 , further comprising:
a dielectric layer comprising a sidewall adjacent the contact, wherein the contact layer extends from the source or drain at least partially along the sidewall.

4. The apparatus of claim 3 , wherein a first thickness of the contact layer on the source or drain is not less than 1.25 times a second thickness of the contact layer along the sidewall or the first thickness and the second thickness differ by not more than 10%.

5. The apparatus of claim 1 , further comprising:
a second channel region between a second source and drain, the second source and drain each comprising silicon and phosphorous; and
a second contact comprising a second layer on at least one of the source or drain, the second layer comprising titanium and silicon.

6. The apparatus of claim 1 , wherein the source and drain each comprise boron doped epitaxial silicon germanium having substantially equal concentrations of silicon and germanium, and the contact layer comprises a thickness of not less than 2 nm and not more than 10 nm.

7. The apparatus of claim 1 , wherein the contact further comprises a second layer and a fill material over the second layer, the second layer comprising titanium and nitrogen, and the fill material comprising at least one of cobalt or tungsten.

8. The apparatus of claim 1 , wherein the channel region, source, drain, and gate electrode are over a substrate layer or a dielectric layer, and wherein the contact extends through an opening in the substrate layer or the dielectric layer.

9. The apparatus of claim 1 , wherein the channel region comprises a region of one of a planar transistor, a multi-gate transistor, or a gate all around transistor.

10. The apparatus of claim 1 , further comprising:
a power supply; and
an integrated circuit die coupled to the power supply, the integrated circuit die comprising the channel region, the source, the drain, the gate electrode, and the contact.

11. An apparatus, comprising:
a channel region between a source and a drain, the source and the drain each comprising silicon and germanium;
a gate electrode adjacent to the channel region; and
a contact comprising a contact layer on at least one of the source or the drain, the contact layer comprising titanium, silicon, and germanium comprising an average germanium concentration of not more than 2.5% through a thickness of the contact layer.

12. The apparatus of claim 11 , wherein the average germanium concentration of the contact layer comprises a germanium concentration of not more than 1% at any position through the thickness of the contact layer.

13. The apparatus of claim 11 , further comprising:
a dielectric layer comprising a sidewall adjacent the contact, wherein the contact layer extends from the source or drain at least partially along the sidewall.

14. The apparatus of claim 13 , wherein a first thickness of the contact layer on the source or drain is not less than 1.25 times a second thickness of the contact layer along the sidewall or the first thickness and the second thickness differ by not more than 10%.

15. The apparatus of claim 11 , further comprising:
a second channel region between a second source and drain, the second source and drain each comprising silicon and phosphorous; and
a second contact comprising a second layer on at least one of the source or drain, the second layer comprising titanium and silicon.

16. The apparatus of claim 11 , wherein the source and drain each comprise boron doped epitaxial silicon germanium having substantially equal concentrations of silicon and germanium, and the contact layer comprises a thickness of not less than 2 nm and not more than 10 nm.

17. The apparatus of claim 1 , wherein the contact further comprises a second layer and a fill material over the second layer, the second layer comprising titanium and nitrogen, and the fill material comprising at least one of cobalt or tungsten.

18. The apparatus of claim 11 , wherein the channel region, source, drain, and gate electrode are over a substrate layer or a dielectric layer, and wherein the contact extends through an opening in the substrate layer or the dielectric layer.

19. The apparatus of claim 11 , wherein the channel region comprises a region of one of a planar transistor, a multi-gate transistor, or a gate all around transistor.

20. The apparatus of claim 11 , further comprising:
a power supply; and
an integrated circuit die coupled to the power supply, the integrated circuit die comprising the channel region, the source, the drain, the gate electrode, and the contact.

Assignees

• Intel Corp

Inventors

• Nandi Debaleena
• Choi Chi-Hing
• Dewey Gilbert
• Kennel Harold
• Saadat Omair
• Jha Jitendra Kumar
• Oni Adedapo
• Haratipour Nazila
• Murthy Anand
• Ghani Tahir

Classifications

• H10D64/011

  of electrodes ohmically coupled to a semiconductor · CPC title

• H10W20/066

  by forming silicides of refractory metals · CPC title

• H10W20/033

  in openings in dielectrics · CPC title

• H10W20/047

  by introducing additional elements therein · CPC title

• H10W20/40

  Interconnections external to wafers or substrates, e.g. back-end-of-line [BEOL] metallisations or vias connecting to gate electrodes · CPC title