DBI to Si bonding for simplified handle wafer

Patent metadata

Field	Value
Publication number	US-12438122-B2
Application number	US-202318464982-A
Country	US
Kind code	B2
Filing date	Sep 11, 2023
Priority date	Apr 20, 2018
Publication date	Oct 7, 2025
Grant date	Oct 7, 2025

Abstract

Devices and techniques include process steps for preparing various microelectronic components for bonding, such as for direct bonding without adhesive. The processes include providing a first bonding surface on a first surface of the microelectronic components, bonding a handle to the prepared first bonding surface, and processing a second surface of the microelectronic components while the microelectronic components are gripped at the handle. In some embodiments, the processes include removing the handle from the first bonding surface, and directly bonding the microelectronic components at the first bonding surface to other microelectronic components.

First claim

What is claimed is:

1. A method comprising:
preparing a bonding surface of a first bonding layer on a substrate;
direct bonding a first side of each of a plurality of dies to the bonding surface using a direct non-adhesive technique to form at least a portion of a structure;
while the substrate supports the plurality of dies, processing a second side of each of the plurality of dies, wherein the second side is opposite the first side;
after processing the second side of each of the plurality of dies, removing at least the substrate by grinding or polishing the substrate to expose a surface of each of the plurality of dies;
applying a first protective coating over the surface and a second protective coating over the first protective coating, wherein the first protective coating is formed of a first material and the second protective coating is formed of a second material that is different than the first material; and
after removing the substrate, singulating the structure to form a plurality of microelectronic units, wherein each of the plurality of microelectronic units comprises at least one of the plurality of dies.

2. The method of claim 1 , wherein processing the second side of each of the plurality of dies comprises thinning each of the plurality of dies to less than 20 microns while the plurality of dies is bonded to the substrate.

3. The method of claim 1 , further comprising plasma activating the bonding surface of the substrate.

4. The method of claim 1 , wherein processing the second side of each of the plurality dies comprises planarizing the second side of each of the plurality of dies.

5. The method of claim 1 , wherein the first side of each of the plurality of dies comprises an oxide and includes one or more conductive interconnects.

6. The method of claim 1 , wherein the substrate comprises silicon.

7. The method of claim 6 , wherein the first bonding layer on the substrate comprises an oxide layer of less than 10 nm formed on the silicon and wherein the oxide layer at least partially defines the bonding surface.

8. The method of claim 7 , wherein the oxide layer is formed on the silicon by thermal oxidation.

9. The method of claim 1 , wherein preparing the bonding surface of the substrate comprises planarizing the bonding surface.

10. The method of claim 1 , wherein the plurality of dies comprises a first die, the method further comprising:
direct bonding a second die to a bonding layer on the first die.

11. The method of claim 10 , wherein the bonding layer on the first die comprises a first conductive feature, wherein the second die comprises a second conductive feature, and wherein the second conductive feature is vertically aligned with and directly bonded to the first conductive feature.

12. The method of claim 10 , wherein direct bonding the second die to the bonding layer on the first die comprises hybrid bonding the second die to the bonding layer on the first die.

13. A method comprising:
direct bonding a plurality of dies to a first bonding layer on a substrate using a permanent direct non-adhesive technique, wherein the plurality of dies comprises a first die;
while the substrate supports the plurality of dies, planarizing a first surface of each of the plurality of dies and providing a second bonding layer on the first surfaces, wherein the first surfaces face away from the substrate;
removing at least the substrate by grinding or polishing to expose a second surface of each of the plurality of dies;
applying a first protective coating over the second surface and a second protective coating over the first protective coating, wherein the first protective coating is formed of a first material and the second protective coating is formed of a second material that is different than the first material; and
direct bonding a second die to the second bonding layer on the first die using a direct bonding technique without an adhesive, wherein the second bonding layer on the first die comprises a first conductive feature and the second die comprises a second conductive feature directly bonded to the first conductive feature.

14. The method of claim 13 , wherein direct bonding the plurality of dies to the substrate comprises direct bonding the plurality of dies to the substrate to form at least a portion of a bonded structure, the method further comprising singulating the bonded structure into a plurality of microelectronic units.

15. The method of claim 14 , wherein the plurality of microelectronic units comprises a first microelectronic unit that includes the first and second dies, the method further comprising stacking and bonding the first microelectronic unit to a prepared host die, wafer, or substrate using a direct bonding technique without adhesive.

16. The method of claim 14 , wherein forming the first and second protective coatings comprises forming the first and second protective coatings before singulating the bonded structure.

17. The method of claim 13 , further comprising, before planarizing the first surfaces of the plurality of dies, thinning the each of the plurality of dies to form the first surfaces.

18. The method of claim 13 , further comprising depositing an insulating layer at the first surfaces to at least partially form the second bonding layer.

19. The method of claim 13 , wherein the first conductive feature is vertically aligned with the second conductive feature.

20. The method of claim 13 , wherein direct bonding the plurality of dies to the substrate using a permanent direct dielectric-to-dielectric non-adhesive technique comprises forming a permanent bond between a dielectric layer on the substrate and each of the plurality of dies, and wherein removing the substrate includes removing the dielectric layer on the substrate used to form the permanent bond.

21. The method of claim 13 , further comprising:
plasma activating at least one of the substrate and the first die before directly bonding the plurality of dies to the substrate.

22. A method comprising:
providing a bonded structure comprising a microelectronic component directly bonded to a bonding layer on a substrate using a direct non-adhesive technique;
while the substrate supports the microelectronic component, processing the microelectronic component to form a first surface on the microelectronic component, wherein the first surface faces away from the substrate;
after processing the microelectronic component to form the first surface, removing at least the substrate to expose a second surface of the microelectronic component;
applying a first protective coating over the second surface and a second protective coating over the first protective coating, wherein the first protective coating is formed of a first material and the second protective coating is formed of a second material that is different than the first material; and
after applying the first and second protective coatings, singulating the bonded structure to form a plurality of microelectronic units, wherein at least one of the plurality of microelectronic units comprises the microelectronic component.

23. The method of claim 22 , wherein the microelectronic component comprises one or more conductive features formed at the second surface.

24. The method of claim 22 , wherein processing the microelectronic component comprises, before removing the substrate, planarizing the first surface.

25. The method of claim 22 , wherein processing th

Assignees

• Adeia Semiconductor Bonding Technologies Inc

Inventors

• Mandalapu Chandrasekhar
• Fountain Jr Gaius Gillman
• Gao Guilian

Classifications

• H10W72/921

  Structures or relative sizes of bond pads · CPC title

• H10W72/923

  Bond pads having multiple stacked layers · CPC title

• H10W90/00

  Package configurations · CPC title

• H10W80/312

  characterised by the direct bonding of electrically conductive pads · CPC title

• H10W80/327

  characterised by the direct bonding of insulating parts, e.g. of silicon oxide layers · CPC title