High throughput additive manufacturing for integrated circuit components containing traces with feature size and grain boundaries

Patent metadata

Field	Value
Publication number	US-12438087-B2
Application number	US-202117484281-A
Country	US
Kind code	B2
Filing date	Sep 24, 2021
Priority date	Sep 24, 2021
Publication date	Oct 7, 2025
Grant date	Oct 7, 2025

Abstract

Technologies for high throughput additive manufacturing (HTAM) structures are disclosed. In one embodiment, a sacrificial dielectric is formed to provide a negative mask on which to pattern a conductive trace using HTAM. In another embodiment, a permanent dielectric is patterned using a processing such as laser project patterning. A conductive trace can then be patterned using HTAM. In yet another embodiment, conductive traces with tapered sidewalls can be patterned, and then a buffer layer and HTAM layer can be deposited on top.

First claim

The invention claimed is:

1. An integrated circuit component comprising:
a substrate; and
one or more conductive traces on the substrate,
wherein individual conductive traces of the one or more conductive traces have a feature size less than 50 micrometers,
wherein individual conductive traces of the one or more conductive traces comprise a plurality of grains separated by grain boundaries, wherein individual grains of the plurality of grains of individual conductive traces of the one or more conductive traces have a diameter between 10 and 100 micrometers,
wherein individual conductive traces of the one or more conductive traces have a thickness of at least 50 micrometers.

2. The integrated circuit component of claim 1 , wherein void spaces are defined between individual conductive traces of the one or more conductive traces.

3. The integrated circuit component of claim 1 , wherein individual conductive traces of the one or more conductive traces comprise copper.

4. The integrated circuit component of claim 3 , wherein individual conductive traces of the one or more conductive traces comprise silicon carbide particles.

5. The integrated circuit component of claim 3 , wherein individual conductive traces of the one or more conductive traces comprise diamond particles.

6. The integrated circuit component of claim 3 , wherein individual conductive traces of the one or more conductive traces comprise aluminum nitride particles.

7. The integrated circuit component of claim 3 , wherein individual conductive traces of the one or more conductive traces comprise boron nitride particles.

8. The integrated circuit component of claim 1 , further comprising a buffer layer between the substrate and the one or more conductive traces.

9. The integrated circuit component of claim 1 , wherein the one or more conductive traces are defined on a surface layer of a circuit board.

10. The integrated circuit component of claim 1 , further comprising a die mated to a circuit board, wherein the one or more conductive traces are defined on a front side of the die.

11. The integrated circuit component of claim 1 , wherein the substrate is an active semiconductor die.

12. The integrated circuit component of claim 1 , wherein the substrate is a passive semiconductor die.

13. The integrated circuit component of claim 1 , wherein the substrate is a reusable carrier.

14. The integrated circuit component of claim 1 , wherein the substrate is an organic package.

15. The integrated circuit component of claim 1 , wherein the substrate is an inorganic package.

16. A system comprising the integrated circuit component of claim 1 , wherein the integrated circuit component is a processor, further comprising:
a circuit board, the processor mated to the circuit board; and
a memory mated to the circuit board and communicatively coupled to the processor.

17. A method comprising:
depositing one or more sacrificial dielectric traces on a substrate for an integrated circuit component;
depositing a conductive layer on the one or more sacrificial dielectric traces using cold spray;
planarizing the conductive layer to expose the one or more sacrificial dielectric traces; and
removing the one or more sacrificial dielectric traces without removing the conductive layer,
wherein the conductive layer forms one or more conductive traces for the integrated circuit component.

18. The method of claim 17 , wherein the conductive layer comprises a plurality of grains separated by grain boundaries, wherein individual grains of the plurality of grains have a diameter between 10 and 100 micrometers.

19. The method of claim 17 , wherein depositing the one or more sacrificial dielectric traces comprises depositing the one or more sacrificial dielectric traces using inkjet printing.

20. The method of claim 17 , wherein depositing the one or more sacrificial dielectric traces comprises depositing the one or more sacrificial dielectric traces using laser patterning.

21. The method of claim 17 , wherein depositing the one or more sacrificial dielectric traces comprises depositing the one or more sacrificial dielectric traces using grayscale lithography.

22. The method of claim 17 , further comprising depositing a buffer layer over the one or more sacrificial dielectric traces and the substrate before depositing the conductive layer.

23. The method of claim 22 , wherein depositing the buffer layer comprises:
sputtering a thin film on the one or more sacrificial dielectric traces and the substrate; and
electroplating the thin film.

24. An integrated circuit component comprising:
a substrate; and
one or more conductive traces on the substrate,
wherein individual conductive traces of the one or more conductive traces have a feature size less than 50 micrometers,
wherein individual conductive traces of the one or more conductive traces have a thickness of at least 50 micrometers,
wherein void spaces are defined between individual conductive traces of the one or more conductive traces.

25. The integrated circuit component of claim 24 , wherein individual conductive traces of the one or more conductive traces comprise a plurality of grains separated by grain boundaries, wherein individual grains of the plurality of grains of individual conductive traces of the one or more conductive traces have a diameter between 10 and 100 micrometers.

Assignees

• Intel Corp

Inventors

• Elsherbini Adel
• Aleksov Aleksandar
• Eid Feras
• Li Wenhao
• Morein Stephen
• Tomita Yoshihiro

Classifications

• H10W20/071

  of dielectric parts thereof · CPC title

• H10W20/062

  by smoothing of conductive parts, e.g. by planarisation · CPC title

• H10W20/032

  of conductive barrier, adhesion or liner layers · CPC title

• H10W70/611

  for connecting multiple chips together · CPC title

• H10W70/685

  comprising multiple insulating layers · CPC title