Package Structures and Methods for Forming the Same

Patent metadata

Field	Value
Publication number	US-2016268145-A1
Application number	US-201615157752-A
Country	US
Kind code	A1
Filing date	May 18, 2016
Priority date	Mar 7, 2013
Publication date	Sep 15, 2016
Grant date	—

Abstract

A packaging structure and a method of forming a packaging structure are provided. The packaging structure, such as an interposer, is formed by optionally bonding two carrier substrates together and simultaneously processing two carrier substrates. The processing includes forming a sacrificial layer over the carrier substrates. Openings are formed in the sacrificial layers and pillars are formed in the openings. Substrates are attached to the sacrificial layer. Redistribution lines may be formed on an opposing side of the substrates and vias may be formed to provide electrical contacts to the pillars. A debond process may be performed to separate the carrier substrates. Integrated circuit dies may be attached to one side of the redistribution lines and the sacrificial layer is removed.

First claim

What is claimed is:

1 . A method comprising:
forming a patterned sacrificial layer over a first substrate, the patterned sacrificial layer having openings formed therein; after forming the patterned sacrificial layer, forming conductive pillars in the openings of the patterned sacrificial layer; after forming the conductive pillars, electrically coupling one or more integrated circuit dies to the conductive pillars; and after electrically coupling the one or more integrated circuit dies to the conductive pillars, removing the patterned sacrificial layer, thereby exposing sidewalls of the conductive pillars.

2 . The method of claim 1 , wherein the first substrate comprises a first carrier substrate and a dielectric layer over the first carrier substrate.

3 . The method of claim 2 , wherein the first substrate further comprises a conductive layer, the dielectric layer being interposed between the conductive layer and the first carrier substrate.

4 . The method of claim 3 , wherein the conductive layer comprises a conductive foil.

5 . The method of claim 4 , wherein the conductive layer is attached to the dielectric layer by an adhesive.

6 . The method of claim 3 , wherein after forming the patterned sacrificial layer, the forming the conductive pillar comprises performing a electroplating process or electrochemical process to form a conductive material in the openings.

7 . The method of claim 6 , further comprising performing a planarization process to remove conductive material from an outer surface of the patterned sacrificial layer.

8 . A method comprising:
forming a first layer over a first surface of a first substrate; forming a second layer over the first layer; forming a first opening in the second layer; after forming the second layer, forming a conductive element in the first opening attaching a second substrate to the second layer such that the second layer is interposed between the second substrate and the first substrate; after attaching the second substrate, forming an electrical connection through the second substrate to the conductive element; electrically coupling one or more integrated circuit dies to the conductive element, the integrated circuit dies being coupled to a side of the second substrate opposite the conductive element; removing the first substrate; and removing the first layer, thereby exposing sidewalls of the conductive element.

9 . The method of claim 8 , wherein the first layer comprises a dielectric layer.

10 . The method of claim 8 , wherein after forming the conductive element, an exposed surface of the second layer and an exposed surface of the conductive element are level.

11 . The method of claim 8 , wherein the second substrate comprises a laminated substrate.

12 . The method of claim 8 , wherein the second substrate comprises an Ajinimoto buildup film (ABF), glass, silicon oxide, aluminum oxide, or a combination thereof.

13 . The method of claim 8 , wherein forming the electrical connection comprises:
after attaching the second substrate, forming a second opening through the second substrate; and depositing a conductive material in the second opening.

14 . A method comprising:
forming a first sacrificial layer on a first carrier substrate and a second sacrificial layer on a second carrier substrate, the first carrier substrate being bonded to the second carrier substrate, the first carrier substrate and the second carrier substrate being interposed between the first sacrificial layer and the second sacrificial layer; patterning the first sacrificial layer to form first openings and the second sacrificial layer to form second openings; filling the first openings and the second openings with a conductive material, thereby forming first pillars and second pillars, respectively; attaching a first interposer substrate on the first sacrificial layer and a second interposer substrate on the second sacrificial layer; forming first through vias through the first interposer substrate to respective ones of the first pillars and second through vias through the second interposer substrate to respective ones of the second pillars; separating the first carrier substrate and the second carrier substrate; and after the separating, removing the first sacrificial layer to expose sidewalls of the first pillars.

15 . The method of claim 14 , prior to removing the first sacrificial layer, placing solder on the first pillars.

16 . The method of claim 14 , after removing the first sacrificial layer, placing solder on the first pillars.

17 . The method of claim 16 , wherein the solder extends along sidewalls of the first pillars.

18 . The method of claim 14 , wherein forming the first sacrificial layer on a first carrier substrate comprises:
forming a dielectric layer over the first carrier substrate; and forming a conductive layer over the dielectric layer, wherein the first sacrificial layer is formed over the conductive layer.

19 . The method of claim 14 , wherein the first sacrificial layer and the second sacrificial layer are formed of polybenzoxazole (PBO) or polyimide.

20 . The method of claim 14 , wherein the first sacrificial layer and the second sacrificial layer are formed of a polymer-based material.

Assignees

• Taiwan Semiconductor Mfg Co Ltd

Inventors

• Meng Hsien-Liang
• Lin Wei-Hung
• Liang Jimmy
• Ho Ming-Che
• Kuo Hung-Jui
• Liu Chung-Shi
• Lii Mirng-Ji

Classifications

• H10W74/142

  the encapsulations exposing the passive side of the semiconductor body · CPC title

• H10W72/073

  of die-attach connectors · CPC title

• H10W72/072

  of bump connectors · CPC title

• H10W90/00

  Package configurations · CPC title

• H10W72/07236

  Soldering or alloying · CPC title