MIM capacitor structure and fabricating method of the same

Patent metadata

Field	Value
Publication number	US-12432946-B2
Application number	US-202318107521-A
Country	US
Kind code	B2
Filing date	Feb 9, 2023
Priority date	Dec 21, 2022
Publication date	Sep 30, 2025
Grant date	Sep 30, 2025

Abstract

An MIM capacitor structure includes numerous inter-metal dielectrics. A trench is embedded within the inter-metal dielectrics. A capacitor is disposed within the trench. The capacitor includes a first electrode layer, a capacitor dielectric layer and a second electrode layer. The first electrode layer, the capacitor dielectric layer and the second electrode layer fill in and surround the trench. The capacitor dielectric layer is between the first electrode layer and the second electrode layer. A silicon oxide liner surrounds a sidewall of the trench and contacts the first electrode layer.

First claim

What is claimed is:

1. A fabricating method of a metal-insulator-metal (MIM) capacitor structure, comprising:
providing a plurality of inter-metal dielectrics;
forming a trench embedded within the plurality of inter-metal dielectrics;
performing a flowable chemical vapor deposition to form a silicon oxide liner covering and contacting the trench and covering and contacting a topmost surface of the plurality of inter-metal dielectrics; and
forming a first electrode layer, a capacitor dielectric layer, a second electrode layer and a copper material layer filling into the trench, wherein the plurality of inter-metal dielectrics comprise a dielectric layer and a stop layer stacked alternately, and wherein along a sidewall of the trench, an end of the stop layer protrudes from an end of the dielectric layer.

2. The fabricating method of an MIM capacitor structure of claim 1 , wherein an operating temperature of the flowable chemical vapor deposition is between 150 degrees Celsius and 200 degrees Celsius.

3. The fabricating method of an MIM capacitor structure of claim 1 , wherein part of a copper dual damascene structure is embedded within the silicon oxide liner.

4. The fabricating method of an MIM capacitor structure of claim 1 , further comprising a plurality of copper dual damascene structures embedded within the plurality of inter-metal dielectrics.

Assignees

• United Microelectronics Corp

Inventors

• Lin da-jun
• Tsai Bin-Siang
• Tsai Fu-Yu
• Chiu Chung-Yi

Classifications

• H10P14/43

  Chemical deposition, e.g. chemical vapour deposition [CVD] · CPC title

• H10W20/4421

  the principal metal being copper · CPC title

• H10W20/056

  by filling conductive material into holes, grooves or trenches · CPC title

• H10W20/47

  comprising two or more dielectric layers having different properties, e.g. different dielectric constants · CPC title

• H10W20/42

  Vias, e.g. via plugs · CPC title