Through via electrode and device isolation structure including oxide layer pattern and nitride layer pattern sequentially stacked on inner surface of trench

Patent metadata

Field	Value
Publication number	US-11735498-B2
Application number	US-202117213767-A
Country	US
Kind code	B2
Filing date	Mar 26, 2021
Priority date	Jul 20, 2020
Publication date	Aug 22, 2023
Grant date	Aug 22, 2023

Abstract

A semiconductor includes a substrate having a first surface and a second surface opposite to each other, the substrate having a via hole extending in a thickness direction from the first surface, a circuit pattern in the first surface of the substrate, a through electrode structure in the via hole, a device isolation structure in a first trench extending in one direction in the first surface of the substrate, the device isolation structure between the via hole and the circuit pattern, the device isolation structure including a first oxide layer pattern and a first nitride layer pattern sequentially stacked on an inner surface of the first trench, the first nitride layer pattern filling the first trench, and an insulation interlayer on the first surface of the substrate and covering the circuit pattern.

First claim

What is claimed is:

1. A semiconductor device, comprising:
a substrate having a first surface and a second surface opposite to each other, the substrate having a via hole extending in a thickness direction from the first surface;
a circuit pattern in the first surface of the substrate;
a through electrode structure in the via hole;
a first device isolation structure in a first trench extending in one direction in the first surface of the substrate, the first device isolation structure between the via hole and the circuit pattern, the first device isolation structure including a first oxide layer pattern and a first nitride layer pattern sequentially stacked on an inner surface of the first trench, the first nitride layer pattern filling the first trench, and an upper surface of the first nitride layer pattern coplanar with an upper surface of the substrate and an upper surface of the first oxide layer pattern;
a second device isolation structure in a second trench encompassing the through electrode structure, the second device isolation structure including a second oxide layer pattern on an inner surface of the second trench, a second nitride layer pattern on the second oxide layer pattern, and a third oxide layer pattern on the second nitride layer pattern, each of the second oxide layer pattern, the second nitride layer pattern, and the third oxide layer pattern of the second device isolation structure contracting a sidewall of the through electrode structure; and
an insulation interlayer on the first surface of the substrate and covering the circuit pattern.

2. The semiconductor device of claim 1 , wherein the circuit pattern is on an active pattern in a circuit region defined by the first trench.

3. The semiconductor device of claim 1 , wherein the first trench is spaced apart from the via hole by a distance of between 5 μm to 15 μm.

4. The semiconductor device of claim 1 , wherein a ratio (D/W 1 ) of a diameter D of the via hole to a width W 1 of the first trench is within a range of 50 to 150.

5. The semiconductor device of claim 1 , wherein the first oxide layer pattern is on the inner surface of the first trench, and the first nitride layer pattern is on the first oxide layer pattern, the first nitride layer pattern filling a remaining portion of the first trench.

6. The semiconductor device of claim 1 , further comprising:
at least one dummy isolation structure in at least one third trench extending in one direction in the first surface of the substrate, the at least one dummy isolation structure between the via hole and the first trench, the at least one dummy isolation structure including a fourth oxide layer pattern and a third nitride layer pattern sequentially stacked on an inner surface of the second trench, the third nitride layer pattern filling the third trench.

7. The semiconductor device of claim 6 , wherein the first oxide layer pattern and the fourth oxide layer pattern include a same first insulation material, and the first nitride layer pattern and the third nitride layer pattern include a same second insulation material.

8. The semiconductor device of claim 1 , wherein the first device isolation structure further comprises an oxide layer pattern on the first nitride layer pattern, the oxide layer pattern filling a remaining portion of the first trench.

9. The semiconductor device of claim 1 , wherein the first oxide layer pattern and the third oxide layer pattern include a same first insulation material, and the first nitride layer pattern and the second nitride layer pattern include a same second insulation material.

10. A semiconductor device, comprising:
a substrate having a first region and a second region;
a circuit pattern in the first region of the substrate;
a through electrode structure penetrating through at least a portion of the second region of the substrate;
a first isolation structure in a first trench, the first isolation structure extending in one direction in the substrate and defining the first region, the first isolation structure including a first oxide layer pattern and a first nitride layer pattern sequentially stacked on an inner surface of the first trench, the first nitride layer pattern filling the first trench, and an upper surface of the first nitride layer pattern coplanar with an upper surface of the substrate and an upper surface of the first oxide layer pattern;
a second isolation structure in a second trench encompassing the through electrode structure, the second isolation structure including a second oxide layer pattern on an inner surface of the second trench, a second nitride layer pattern on the first oxide layer pattern, and a third oxide layer pattern on the second nitride layer pattern, each of the second oxide layer pattern, the second nitride layer pattern, and the third oxide layer pattern of the second isolation structure contacting a sidewall of the through electrode structure; and
an insulation interlayer on the substrate and covering the circuit pattern.

11. The semiconductor device of claim 10 , wherein the circuit pattern is on an active pattern, the active pattern in the first region.

12. The semiconductor device of claim 10 , wherein the first trench is spaced apart from the through electrode structure by a distance of between 5 μm to 15 μm.

13. The semiconductor device of claim 10 , wherein a ratio (D/W 1 ) of a diameter D of the through electrode structure to a width W 1 of the first trench is within a range of 50 to 150.

14. The semiconductor device of claim 10 , further comprising:
at least one third isolation structure in at least one third trench extending in one direction in the substrate, the at least one third isolation structure in a third region between the first region and the second region, the at least one third isolation structure including a fourth oxide layer pattern and a third nitride layer pattern sequentially stacked on an inner surface of the third trench, the third nitride layer pattern filling the third trench.

15. The semiconductor device of claim 14 , wherein the first oxide layer pattern and the fourth oxide layer pattern include a same first insulation material, and the first nitride layer pattern and third nitride layer pattern include a same second insulation material.

16. The semiconductor device of claim 10 , wherein the second
isolation structure in the second trench defines the second region, and
the third oxide layer pattern fills a remaining portion of the second trench.

17. The semiconductor device of claim 16 , wherein the first oxide layer pattern and the second oxide layer pattern include a same first insulation material, and the first nitride layer pattern and the second nitride layer pattern include a same second insulation material.

18. The semiconductor device of claim 10 , wherein the through electrode structure comprises a through electrode and a via insulation layer pattern surrounding a sidewall of the through electrode.

19. A semiconductor device, comprising:
a substrate having a circuit region, a via region, and a buffer region between the circuit region and the via region;
a circuit pattern in the circuit region of the substrate;
a through electrode structure penetrating at least a portion of the via region of the substrate;
a device isolation structure in a first trench extending in one direction in the substrate, the device isolation structure defining the circuit region, and including a first oxide layer pattern on an inner surface of the first trench and a first nitride layer pattern on the

Assignees

• Samsung Electronics Co Ltd

Inventors

• Park Kwangwuk
• Lee Youngmin
• Cho Sungdong
• Kim Eunji
• Mun Hyoungyol
• Jeong Seokhwan

Classifications

• H10W20/0245

  comprising use of blind vias during the manufacture · CPC title

• H10W20/2134

  TSVs extending from the semiconductor wafer into back-end-of-line layers · CPC title

• H10W20/0265

  characterised by the sidewall insulation · CPC title

• H10W10/0145

  of trenches having shapes other than rectangular or V-shape (H10W10/0143 takes precedence) · CPC title

• H10W10/17

  formed using trench refilling with dielectric materials, e.g. shallow trench isolations · CPC title