Three-dimensional memory devices and methods for forming the same

Patent metadata

Field	Value
Publication number	US-12432918-B2
Application number	US-202217570091-A
Country	US
Kind code	B2
Filing date	Jan 6, 2022
Priority date	Aug 23, 2021
Publication date	Sep 30, 2025
Grant date	Sep 30, 2025

Abstract

A three-dimensional (3D) memory device includes a stack structure having interleaved conductive layers and dielectric layers, and a channel structure extending through the stack structure along a first direction. The channel structure is in contact with a source of the 3D memory device at a bottom portion of the channel structure. The channel structure includes a semiconductor channel, and a memory film over the semiconductor channel. The memory film includes a tunneling layer over the semiconductor channel, a storage layer over the tunneling layer, and a blocking layer over the storage layer. A first thickness of the bottom portion of the channel structure is larger than a second thickness of a top portion of the channel structure.

First claim

What is claimed is:

1. A three-dimensional (3D) memory device, comprising:
a stack structure comprising interleaved conductive layers and dielectric layers;
a channel structure extending through the stack structure along a first direction in contact with a source of the 3D memory device at a bottom portion of the channel structure, the channel structure comprising a semiconductor channel, and a memory film over the semiconductor channel, and the memory film comprising a tunneling layer over the semiconductor channel, a storage layer over the tunneling layer, and a blocking layer over the storage layer; and
a polysilicon layer disposed under the stack structure,
wherein a first thickness of the blocking layer at the bottom portion of the channel structure is larger than a second thickness of the blocking layer at an upper portion of the channel structure, and the first thickness of the blocking layer or the second thickness of the blocking layer comprises dielectric materials formed between the storage layer and the stack structure along a second direction perpendicular to the first direction; and
the tunneling layer, the storage layer, and the blocking layer are in direct contact with the polysilicon layer.

2. The 3D memory device of claim 1 , wherein the semiconductor channel comprises an angled structure, and a first diameter of the semiconductor channel at the bottom portion of the channel structure below the angled structure is smaller than a second diameter of the semiconductor channel at the upper portion of the channel structure above the angled structure.

3. The 3D memory device of claim 1 ,
wherein the polysilicon layer is in direct contact with the semiconductor channel.

4. The 3D memory device of claim 3 , wherein the polysilicon layer is in direct contact with a bottom surface of the semiconductor channel and a portion of a side surface of the semiconductor channel at the bottom portion of the channel structure.

5. The 3D memory device of claim 4 , wherein the bottom surface of the semiconductor channel is above a bottom surface of the stack structure.

6. The 3D memory device of claim 4 , wherein the bottom surface of the semiconductor channel is beneath a bottom surface of the stack structure.

7. The 3D memory device of claim 3 , wherein a bottom surface of the memory film is above the bottom surface of the semiconductor channel.

8. The 3D memory device of claim 1 , wherein the memory film comprises a bending portion at the bottom portion of the channel structure.

9. A three-dimensional (3D) memory device, comprising:
a stack structure comprising interleaved conductive layers and dielectric layers;
a channel structure extending through the stack structure along a first direction in contact with a source of the 3D memory device at a bottom portion of the channel structure, the channel structure comprising a semiconductor channel, and a memory film over the semiconductor channel, and the memory film comprising a tunneling layer over the semiconductor channel, a storage layer over the tunneling layer, and a blocking layer over the storage layer; and
a polysilicon layer disposed under the stack structure,
wherein the semiconductor channel comprises an angled structure, and a first diameter of the semiconductor channel at the bottom portion of the channel structure below the angled structure is smaller than a second diameter of the semiconductor channel at an upper portion of the channel structure above the angled structure; and
the tunneling layer, the storage layer, and the blocking layer are in direct contact with the polysilicon layer.

10. The 3D memory device of claim 9 ,
wherein the polysilicon layer is in direct contact with the semiconductor channel.

11. The 3D memory device of claim 10 , wherein the polysilicon layer is in direct contact with a bottom surface of the semiconductor channel and a portion of a side surface of the semiconductor channel at the bottom portion of the channel structure.

12. The 3D memory device of claim 11 , wherein the bottom surface of the semiconductor channel is above a bottom surface of the stack structure.

13. The 3D memory device of claim 11 , wherein the bottom surface of the semiconductor channel is beneath a bottom surface of the stack structure.

14. The 3D memory device of claim 9 , wherein the semiconductor channel comprises a bending portion at the bottom portion of the channel structure.

15. A method for forming a three-dimensional (3D) memory device, comprising:
forming a first stack structure comprising a first dielectric layer, a first polysilicon layer, a second dielectric layer, and a second polysilicon layer on a substrate;
forming a second stack structure comprising a plurality of third dielectric layers and a plurality of sacrificial layers alternatingly arranged on the first stack structure;
forming a channel hole penetrating the second stack structure and the first stack structure along a first direction;
performing an oxidation operation to form a fourth dielectric layer on the first polysilicon layer exposed by sidewalls of the channel hole;
forming a channel structure in the channel hole;
removing the substrate, the first dielectric layer, the first polysilicon layer, the fourth dielectric layer, and a bottom portion of the channel structure; and
forming a third polysilicon layer over the channel structure.

16. The method of claim 15 , wherein performing the oxidation operation to form the fourth dielectric layer on the first polysilicon layer exposed by sidewalls of the channel hole, further comprises:
forming the fourth dielectric layer on the first polysilicon layer exposed by sidewalls of the channel hole along a second direction perpendicular to the first direction.

17. The method of claim 16 , wherein performing the oxidation operation to form the fourth dielectric layer on the first polysilicon layer exposed by sidewalls of the channel hole, further comprises:
forming a fifth dielectric layer on the second polysilicon layer exposed by sidewalls of the channel hole along the second direction.

18. The method of claim 16 , wherein the first polysilicon layer is divided by the channel hole into a first portion and a second portion in a cross-sectional view of the 3D memory device, and the fourth dielectric layer formed on the first portion of the first polysilicon layer is in contact with the fourth dielectric layer formed on the second portion of the first polysilicon layer.

19. The method of claim 16 , wherein the first polysilicon layer is divided by the channel hole into a first portion and a second portion in a cross-sectional view of the 3D memory device, and the fourth dielectric layer formed on the first portion of the first polysilicon layer is separate from the fourth dielectric layer formed on the second portion of first polysilicon layer by a gap.

20. The method of claim 15 , further comprising:
performing a pretreatment operation on the first polysilicon layer and the second polysilicon layer.

Assignees

• Yangtze Memory Tech Co Ltd

Inventors

• Wu Linchun
• Zhang Kun
• Zhou Wenxi
• Xia Zhiliang
• Xie Wei
• Wang Di
• Wang Bingguo
• Huo Zongliang

Classifications

• H10B41/35 Primary

  with a cell select transistor, e.g. NAND · CPC title

• H10B43/35

  with cell select transistors, e.g. NAND · CPC title

• H10B41/27 Primary

  the channels comprising vertical portions, e.g. U-shaped channels · CPC title

• H10B43/10

  characterised by the top-view layout · CPC title

• H10B41/10

  characterised by the top-view layout · CPC title