Technologies for high throughput additive manufacturing for integrated circuit components

Patent metadata

Field	Value
Publication number	US-12431430-B2
Application number	US-202117484339-A
Country	US
Kind code	B2
Filing date	Sep 24, 2021
Priority date	Sep 24, 2021
Publication date	Sep 30, 2025
Grant date	Sep 30, 2025

Abstract

Technologies for high throughput additive manufacturing (HTAM) structures are disclosed. In one embodiment, a sacrificial dielectric is formed to provide a negative mask on which to pattern a conductive trace using HTAM. In another embodiment, a permanent dielectric is patterned using a processing such as laser project patterning. A conductive trace can then be patterned using HTAM. In yet another embodiment, conductive traces with tapered sidewalls can be patterned, and then a buffer layer and HTAM layer can be deposited on top.

First claim

The invention claimed is:

1. An integrated circuit component comprising:
a substrate;
one or more conductive traces on the substrate, wherein individual conductive traces of the one or more conductive traces have tapered sidewalls;
one or more buffer stacks over the one or more conductive traces; and
a conductive layer over the one or more buffer stacks,
wherein conductive layer comprises a plurality of grains separated by grain boundaries, wherein individual grains of the plurality of grains of individual conductive traces of the one or more conductive traces have a diameter between 10 and 100 micrometers.

2. The integrated circuit component of claim 1 , wherein individual conductive traces of the one or more conductive traces have tapered sidewalls with a taper angle between 10 and 45 degrees.

3. The integrated circuit component of claim 1 , wherein individual buffer stacks of the one or more buffer stacks comprise a dielectric layer over the one or more conductive traces and a buffer layer over the dielectric layer.

4. The integrated circuit component of claim 3 , wherein the dielectric layer of individual buffer stacks of the one or more buffer stacks comprises (i) silicon and nitrogen, (ii) silicon, carbon, and nitrogen, (iv) titanium and oxygen, (v) hafnium and oxygen, (vi) silicon and oxygen, (vii) aluminum and nitrogen, or (viii) aluminum and oxygen.

5. The integrated circuit component of claim 3 , wherein the buffer layer of individual buffer stacks of the one or more buffer stacks comprises titanium, tantalum, gold, nickel, vanadium, silver, or copper.

6. The integrated circuit component of claim 1 , wherein the conductive layer has a thickness of at least 50 micrometers.

7. The integrated circuit component of claim 1 , wherein the conductive layer comprise copper.

8. The integrated circuit component of claim 7 , wherein the conductive layer comprises silicon carbide particles.

9. The integrated circuit component of claim 7 , wherein the conductive layer comprises diamond particles.

10. The integrated circuit component of claim 7 , wherein the conductive layer comprises aluminum nitride particles.

11. The integrated circuit component of claim 7 , wherein the conductive layer comprises boron nitride particles.

12. The integrated circuit component of claim 1 , wherein the one or more conductive traces are defined on a surface layer of a circuit board.

13. The integrated circuit component of claim 1 , further comprising a die mated to a circuit board, wherein the one or more conductive traces are defined on a backside of the die.

14. The integrated circuit component of claim 1 , further comprising a die mated to a circuit board, wherein the one or more conductive traces are defined on a front side of the die.

15. A system comprising the integrated circuit component of claim 1 , wherein the integrated circuit component is a processor, further comprising:
a circuit board, the processor mated to the circuit board; and
a memory mated to the circuit board and communicatively coupled to the processor.

16. An integrated circuit component comprising:
a substrate;
one or more conductive traces on the substrate, wherein individual conductive traces of the one or more conductive traces have tapered sidewalls;
one or more buffer stacks over the one or more conductive traces; and
a conductive layer over the one or more buffer stacks,
wherein individual buffer stacks of the one or more buffer stacks comprise a dielectric layer over the one or more conductive traces and a buffer layer over the dielectric layer.

17. The integrated circuit component of claim 16 , wherein individual conductive traces of the one or more conductive traces have tapered sidewalls with a taper angle between 10 and 45 degrees.

18. The integrated circuit component of claim 16 , wherein conductive layer comprises a plurality of grains separated by grain boundaries, wherein individual grains of the plurality of grains of individual conductive traces of the one or more conductive traces have a diameter between 10 and 100 micrometers.

19. The integrated circuit component of claim 16 , wherein the conductive layer has a thickness of at least 50 micrometers.

Assignees

• Intel Corp

Inventors

• Tomita Yoshihiro
• Aleksov Aleksandar
• Eid Feras
• Elsherbini Adel
• Li Wenhao
• Morein Stephen

Classifications

• H10W70/65

  Shapes or dispositions of interconnections · CPC title

• H10W20/435

  Cross-sectional shapes or dispositions of interconnections · CPC title

• H10W20/063

  by forming conductive members before forming protective insulating material · CPC title

• H10W20/039

  also covering sidewalls of the conductive structures · CPC title

• H10W20/425 Primary

  Barrier, adhesion or liner layers · CPC title