Monolithic conductive cylinder in a semiconductor device and associated methods

Patent metadata

Field	Value
Publication number	US-12424517-B2
Application number	US-202217670393-A
Country	US
Kind code	B2
Filing date	Feb 11, 2022
Priority date	Feb 11, 2022
Publication date	Sep 23, 2025
Grant date	Sep 23, 2025

Abstract

A semiconductor device having monolithic conductive cylinders, and associated systems and methods, are disclosed herein. The semiconductor device can include a semiconductor substrate, a conductive pad, an opening, and a top dielectric layer. The conductive pad may be at a first surface of the semiconductor substrate. The opening may be ring-shaped and extend through the semiconductor substrate from the conductive pad to a second surface and define a side wall. The liner may coat the side wall and the top dielectric layer may cover the second surface and may fill the opening. A second ring-shaped opening may be formed through the semiconductor device and the opening and a conductive material plated therein.

First claim

We claim:

1. A semiconductor device assembly, comprising:
a base die, including:
a semiconductor substrate including an upper surface,
a base conductive pad at the upper surface, and
a base dielectric layer disposed over the base conductive pad and the upper surface;
a plurality of dies, each including:
a semiconductor substrate including an upper surface and a lower surface,
a conductive pad at the lower surface having a bottom surface opposite the lower surface,
a lower dielectric layer disposed over the conductive pad and the lower surface,
an opening extending through the semiconductor substrate and the conductive pad from the bottom surface to the upper surface, and defining an opening exterior side wall of the semiconductor substrate and side surfaces of the conductive pad,
a portion of the semiconductor substrate disconnected from the semiconductor substrate, disposed within the opening, and defining an opening interior side wall, and
an upper dielectric layer disposed over the upper surface and coating at least the opening exterior side wall, wherein the plurality of dies is stacked over the base die such that the opening of each of the plurality of dies is vertically aligned with the base conductive pad; and

a monolithic conductive cylinder extending from the base conductive pad through the opening of each of the plurality of dies and in direct contact with the side surfaces of the conductive pad of each of the plurality of dies.

2. The semiconductor device assembly of claim 1 , wherein the upper dielectric layer of at least one of the plurality of dies further includes a non-conductive liner coating at least the opening exterior side wall.

3. The semiconductor device assembly of claim 2 , wherein the upper dielectric layer of the at least one of the plurality of dies further includes a portion of a plug of non-conductive material between the monolithic conductive cylinder and the non-conductive liner.

4. The semiconductor device assembly of claim 1 , wherein the semiconductor substrate of the base die further includes a lower surface opposite the upper surface and the semiconductor device assembly further comprises:
an external connector assembly, including:
an external conductive column extending through the base die semiconductor substrate from the upper surface at the conductive pad to the lower surface, and
an electric connector coupled to the lower surface of the base die semiconductor substrate at the external conductive column.

5. The semiconductor device assembly of claim 4 , wherein the semiconductor device assembly is configured such that the electric connector is in electric communication with each of the plurality of dies via the external conductive column, the base conductive pad, the monolithic conductive cylinder, and the conductive pad of each of the plurality of dies.

6. The semiconductor device assembly of claim 1 , wherein the semiconductor device assembly further comprises:
an uppermost die of the plurality of dies as a top die stacked over the base die;
an assembly cover layer disposed over the upper dielectric layer of the uppermost die and including an upper surface; and
an external connector assembly, including:
an external conductive column extending through the assembly cover layer from the upper surface to the uppermost die, and
an electric connector coupled to the upper surface of the assembly cover layer at the external conductive column.

7. The semiconductor device assembly of claim 6 , wherein the semiconductor device assembly is configured such that the electric connector is in electric communication with each of the plurality of dies via the external conductive column, the monolithic conductive cylinder, and the conductive pad of each of the plurality of dies.

8. The semiconductor device assembly of claim 1 , wherein the base die further includes a second base conductive pad at the upper surface and each of the plurality of dies further includes a second conductive pad at the lower surface having a second bottom surface opposite the lower surface and a second opening extending through the semiconductor substrate and the second conductive pad from the second bottom surface to the upper surface, and wherein a second monolithic conductive cylinder extends from the second base conductive pad through the second opening of each of the plurality of dies and in direct contact with side surfaces of the second conductive pad of each of the plurality of dies.

9. A semiconductor device, comprising:
a semiconductor substrate having a first surface and a second surface opposite the first surface;
a conductive pad at the first surface of the semiconductor substrate;
a first dielectric layer disposed over the first surface and the conductive pad;
an opening extending through the semiconductor substrate from the conductive pad at the first surface to the second surface, and defining an opening exterior side wall;
a portion of the semiconductor substrate disconnected from the semiconductor substrate, disposed within the opening, and defining an opening interior side wall; and
a second dielectric layer covering the second surface and filling the opening between the opening exterior side wall and the opening interior side wall.

10. The semiconductor device of claim 9 , further comprising:
a second semiconductor device having a second semiconductor substrate with a top surface and a bottom surface opposite the top surface;
a second conductive pad at the bottom surface of the second semiconductor substrate;
a bottom dielectric layer disposed over the bottom surface and the second conductive pad; and
a second opening extending through the second semiconductor substrate from the second conductive pad to the top surface, wherein the bottom dielectric layer is bonded to the second dielectric layer with the second opening in alignment with the opening.

11. The semiconductor device of claim 9 , wherein a second conductive pad is at the first surface of the semiconductor substrate and a second opening extends through the semiconductor substrate from the second conductive pad to the second surface of the semiconductor substrate.

12. The semiconductor device of claim 11 , wherein the second dielectric layer further fills the second opening from the second conductive pad to the second surface of the semiconductor substrate.

13. The semiconductor device of claim 9 , wherein the second dielectric layer further includes a non-conductive liner coating at least the opening exterior side wall.

14. The semiconductor device of claim 13 , wherein the second dielectric layer further includes a plug of non-conductive material filling the opening.

15. The semiconductor device of claim 14 , wherein at least two of the non-conductive liner, the plug, and the remainder of the second dielectric layer comprise different non-conductive materials.

16. The semiconductor device of claim 9 , wherein the second dielectric layer further includes a plug of a different material than the second dielectric layer filling the opening.

17. A method of manufacturing a semiconductor device assembly, comprising:
providing a plurality of semiconductor devices, each having a semiconductor substrate with a first surface and a second surface, a conductive pad at the first surface, and a first opening extending through the semiconductor substrate from the conductive pad at the first surface to the second surface;
covering the second surface and filling the first opening of each of the plurality of semiconductor devices with a dielectric layer;
stacking the pluralit

Assignees

• Micron Technology Inc

Inventors

• Zhou Wei
• Kirby Kyle K
• Street Bret K
• Parekh Kunal R

Classifications

• H10W20/0238

  comprising etching via holes through pads or through electrodes · CPC title

• H10W20/0265

  characterised by the sidewall insulation · CPC title

• H10W20/2134

  TSVs extending from the semiconductor wafer into back-end-of-line layers · CPC title

• H10W20/2125

  Top-view shapes · CPC title

• H10W20/0242

  comprising etching via holes from the back sides of the chips, wafers or substrates · CPC title