Self-aligned contact openings for backside through substrate vias

Patent metadata

Field	Value
Publication number	US-2021111102-A1
Application number	US-202016948874-A
Country	US
Kind code	A1
Filing date	Oct 5, 2020
Priority date	Oct 11, 2019
Publication date	Apr 15, 2021
Grant date	—

Abstract

A method includes etching a through-substrate via (TSV) in a substrate from a backside of the substrate. The substrate has a device layer on a frontside. The method further includes depositing a conformal spacer layer on the backside of the substrate, and sidewalls and a bottom of the TSV, and etching the spacer layer to form a self-aligned mask for etching a contact opening at the bottom of TSV to a metal pad in the device layer, and etching the contact opening at the bottom of TSV to the metal pad in the device layer. The method further includes disposing a conductive material layer in the TSV and the contact opening to make a vertical interconnection from the backside of the substrate to the metal pad in the device layer.

First claim

What is claimed is:

1 . A method comprising:
etching a through-substrate via (TSV) in a substrate from a backside of the substrate, the substrate having a device layer on a frontside; depositing a conformal spacer layer on the backside of the substrate, and sidewalls and a bottom of the TSV; etching the spacer layer to form a self-aligned mask for etching a contact opening at the bottom of TSV to a metal pad in the device layer, the self-aligned mask being formed by the spacer layer deposited on the sidewalls of the TSV; and etching a contact opening at the bottom of TSV to the metal pad in the device layer.

2 . The method of claim 1 , wherein the spacer layer is made of a silicate glass.

3 . The method of claim 2 , wherein etching the spacer layer includes directional reactive ion etching of the spacer layer leaving the spacer layer deposited on the sidewalls to form the self-aligned mask.

4 . The method of claim 3 , further comprising:
after etching the contact opening, removing the self-aligned mask formed by the spacer layer deposited on sidewalls of the TSV.

5 . The method of claim 4 , further comprising:
after removing the self-aligned mask formed by the spacer layer deposited on sidewalls of the TSV, depositing a conductive material in the TSV and the contact opening to form a vertical interconnection from the backside of the substrate to the metal pad.

6 . The method of claim 1 , wherein the spacer layer is made of a refractory metal.

7 . The method of claim 6 , wherein the refractory metal is one of tungsten, titanium or a combination thereof.

8 . The method of claim 6 , wherein etching the spacer layer includes directional reactive ion etching of the spacer layer leaving the spacer layer deposited on the sidewalls to form the self-aligned mask.

9 . The method of claim 8 , further comprising:
with the self-aligned mask formed by the spacer layer deposited on sidewalls of the TSV in place, depositing a conductive material in the TSV and the contact opening to form a vertical interconnection from the backside of the substrate to the metal pad.

10 . The method of claim 1 , wherein the TSV has a diameter in a range of about 0.5 microns to about 10 microns.

11 . A method, comprising:
etching an annular through-substrate via (TSV) in a substrate from a backside of the substrate, the annular TSV enclosing a cylindrical pillar of substrate material, the substrate having a device layer on a frontside; depositing a polymer or oxide fill material on the backside of the substrate and in the annular TSV; removing the cylindrical pillar of substrate material to form a cylindrical TSV; and making a contact opening through the cylindrical TSV to a metal pad in the device layer.

12 . The method of claim 11 , wherein when removing cylindrical pillar of substrate material to form a cylindrical TSV, the polymer or oxide fill deposited in the annular TSV remains to line sidewalls of the cylindrical TSV.

13 . The method of claim 11 , further comprising:
disposing a conductive material layer in the cylindrical TSV and the contact opening for making an electrical connection from the backside to the metal pad.

14 . The method of claim 11 , wherein the cylindrical TSV has a diameter in a range of about 0.5 microns to about 10 microns.

15 . A structure, comprising:
a first device die including a substrate having a frontside and a backside, and a device layer disposed on the frontside of the substrate, the device layer including a metal pad; a through-substrate via (TSV) extending from the backside of the substrate toward the frontside; a liner disposed on sidewalls the TSV, the liner being made of one of a refractory metal or a polymer; a contact opening extending from a bottom of the TSV to the metal pad; and a conductive material layer disposed in the TSV and the contact opening making a vertical interconnection from the backside of the substrate to the metal pad.

16 . The structure of claim 15 , wherein the TSV has a diameter in a range of about 0.5 microns to about 10 microns.

17 . The structure of claim 15 , wherein the refractory metal includes at least one of tungsten, titanium, molybdenum, or tantalum.

18 . The structure of claim 15 , further comprising:
a second device die stacked on the first device die with a metallization level pad of the second device die bonded to a metallization level pad of the second device die, the vertical interconnection from the backside of the substrate to the metal pad extending into the second device die through the metallization level pad of the first device die bonded to the metallization level pad of the second device die.

19 . The structure of claim 18 , wherein the first device die is a logic device die and the second device die is a memory device die.

20 . The structure of claim 18 , wherein the first device die is a logic device die and the second device die is CMOS-image sensor die.

21 . The structure of claim 20 , wherein the CMOS image sensor die is in a gapless configuration in which a glass layer is attached to the sensor without any in-between air gap.

Assignees

• Semiconductor Components Ind Llc

Inventors

• Gambino Jeffrey Peter
• Borthakur Swarnal

Classifications

• H10W80/00

  Direct bonding of chips, wafers or substrates · CPC title

• H10W20/2134

  TSVs extending from the semiconductor wafer into back-end-of-line layers · CPC title

• H10W20/217

  comprising ring-shaped isolation structures outside of the via holes · CPC title

• H10W20/2125

  Top-view shapes · CPC title

• H10W20/0242

  comprising etching via holes from the back sides of the chips, wafers or substrates · CPC title