Pin assignments based on bandwidth

Patent metadata

Field	Value
Publication number	US-12416956-B2
Application number	US-202017795021-A
Country	US
Kind code	B2
Filing date	Feb 13, 2020
Priority date	Feb 13, 2020
Publication date	Sep 16, 2025
Grant date	Sep 16, 2025

Abstract

In example implementations, an apparatus is provided. The apparatus includes a cable interface, a video interface, an integrated chip, and a controller. The cable interface is to connect a host device via a cable. The video interface is to output video signals corresponding to visual data. The controller is communicatively coupled to the cable interface, the video interface, and the integrated chip. The controller assigns pairs of pins of the cable to transmit video signals based on the bandwidth used by the video signals. The controller also causes the host device to re-assign the pairs of pins of the cable to transmit the video signals.

First claim

The invention claimed is:

1. An apparatus, comprising:
a cable interface to:
receive, while connected with a host device via a cable, video data from pins in the cable;

a video interface to:
transmit, while connected to a display, the video data to the display, and an integrated circuit chip to:
determine, in response to detecting a connection between the video interface and the display, an amount of video bandwidth necessary for transmission of the video data to the display by the video interface based on a refresh rate of a video image included within the video data; and

a controller to:
control, in response to determining the amount of video bandwidth, the host device to reconfigure a current assignment of the pins in the cable based on the determined amount of video bandwidth in response to a determination that the current assignment is insufficient to provide the determined amount of video bandwidth.

2. The apparatus of claim 1 , wherein the cable comprises a universal serial bus type-C (USB-C) cable.

3. The apparatus of claim 2 , wherein the USB-C cable comprises four pairs of high-speed pins, and the four pairs of high-speed pins are assigned to transmit the video data.

4. The apparatus of claim 1 , further comprising:
a 4:6 multiplexer to map pairs of the pins that are re-assigned.

5. The apparatus of claim 1 , further comprising:
the integrated circuit chip to calculate the amount of video bandwidth.

6. The apparatus of claim 5 , wherein the integrated circuit chip comprises a display port multi-streaming transport hub chip of a docking station.

7. The apparatus of claim 5 , wherein the integrated circuit chip comprises a scaler chip of a display.

8. The apparatus of claim 5 , wherein the controller is communicatively coupled to the cable interface, the video interface, and the integrated circuit chip.

9. The apparatus of claim 1 , wherein the controller is to determine the amount of video bandwidth based on characteristics of the video image.

10. The apparatus of claim 1 , wherein the controller is to determine the amount of video bandwidth based on a number of bits of the video image.

11. The apparatus of claim 1 , wherein the controller is to determine the amount of video bandwidth based on a resolution of the display.

12. A method, comprising:
determining, by a processor in response to detecting a connection between a video output and a display, an amount of video bandwidth used by the video output;
determining, by the processor, that the amount of video bandwidth is greater than an available bandwidth of a high-speed cable based on a first pair of pins of the high-speed cable that are assigned to transmit video data;
assigning, by the processor, a second pair of pins of the high-speed cable to transmit the video data based on the amount of video bandwidth;
causing, by the processor, a host device to assign the second pair of pins of the high-speed cable to transmit the video data; and
providing, by the processor, the video data to the video output via the first pair of pins and the second pair of pins of the high-speed cable,
wherein the determining the amount of video bandwidth comprises: receiving, by the processor, the amount of video bandwidth that is used from an integrated circuit chip in communication with the display, and
wherein the integrated circuit chip calculates the amount of bandwidth based on a refresh rate of a video image included within the video data.

13. The method of claim 12 , wherein the amount of video bandwidth is calculated when the display is initially connected to the video output.

14. The method of claim 13 , wherein the amount of video bandwidth is calculated based on a resolution of the display.

15. The method of claim 12 , wherein the causing the host device to assign the second pair of pins comprises:
presenting, by the processor, a single configuration option to the host device that includes the first pair of pins and the second pair of pins of the high-speed cable assigned to transmit the video data.

16. The method of claim 12 , wherein the integrated circuit chip comprises a scaler chip or a display port media stream transport hub chip.

17. A non-transitory computer-readable storage medium encoded with instructions executable by a processor, the non-transitory computer-readable storage medium comprising:
instructions to cause the processor to receive an indication that an amount of bandwidth used by a video output is greater than an available amount of bandwidth on two pairs of pins of a universal serial bus type-C (USB-C) cable;
instructions to cause a host device connected via the USB-C cable to assign two additional pairs of pins of the USB-C cable to transmit video data;
instructions to cause the host device to receive the video data over the two pairs of pins and the two additional pairs of pins of the USB-C cable; and
instructions to cause the host device to transmit the video data to the video output,
wherein the instructions to cause the processor to receive the indication are performed each time a new display is communicatively coupled to an integrated circuit chip that is communicatively coupled to the processor,
wherein the indication comprises receiving, by the processor, the amount of video bandwidth that is used from the integrated circuit chip in communication with a display,
wherein the integrated circuit chip calculates the amount of bandwidth based on a refresh rate of a video image included within the video data.

18. The non-transitory computer-readable storage medium of claim 17 , wherein the two additional pairs of pins of the USB-C cable comprise pin pairs (A 2 , A 3 ), (B 10 , B 11 ), (B 2 , B 3 ), and (A 10 , A 11 ).

Assignees

• Hewlett Packard Development Co
• Hewlett Packard Development Lp

Inventors

• Hsu Hengchang
• Fossati Humberto Mario
• Hsu Ting-Yu

Classifications

• G06F13/102 Primary

  where the program performs an interfacing function, e.g. device driver (G06F13/105 takes precedence; contention policies within device drivers G06F9/4881; scheduling within device drivers G06F9/52) · CPC title

• G06F1/266 Primary

  Arrangements to supply power to external peripherals either directly from the computer or under computer control, e.g. supply of power through the communication port, computer controlled power-strips · CPC title