Configuration of base clock frequency of processor based on usage parameters

Patent metadata

Field	Value
Publication number	US-12416940-B2
Application number	US-202418765128-A
Country	US
Kind code	B2
Filing date	Jul 5, 2024
Priority date	Feb 24, 2017
Publication date	Sep 16, 2025
Grant date	Sep 16, 2025

Abstract

A processing device includes a plurality of processing cores, a control register, associated with a first processing core of the plurality of processing cores, to store a first base clock frequency value at which the first processing core is to run, and a power management circuit to receive a base clock frequency request comprising a second base clock frequency value, store the second base clock frequency value in the control register to cause the first processing core to run at the second base clock frequency value, and expose the second base clock frequency value on a hardware interface associated with the power management circuit.

First claim

What is claimed is:

1. A multi-core processor comprising:
a plurality of processing cores;
a plurality of control registers corresponding to the plurality of processing cores, wherein each control register of the plurality of control registers is associated with a different processing core of the plurality of processing cores, the plurality of control registers to store per-core base clock frequency values corresponding to the plurality of processing cores;
the per-core base clock frequency values initially comprising default per-core base clock frequency values determined by a manufacturer of the multi-core processor; and
power management circuitry to execute firmware to control clock frequencies of the plurality of processing cores based, at least in part, on the per-core base clock frequency values;
the power management circuitry to:
receive target per-core base clock frequency values, at least some of the target per-core base clock frequency values different from corresponding default per-core base clock frequency values;
store the target per-core base clock frequency values in corresponding control registers of the plurality of control registers to cause a corresponding processing core of the plurality of processing cores to operate according to the target per-core base clock frequency values; and
expose the target per-core base clock frequency values to software.

2. The multi-core processor of claim 1 , wherein the target per-core base clock frequency values are determined based, at least in part, on a target service level.

3. The multi-core processor of claim 2 , wherein the target service level is to indicate one or more of: a maximum power to be consumed by all or a subset of the plurality of processing cores, a thermal design power (TDP) value, and exclusivity to use one or more particular processing cores of the plurality of processing cores.

4. The multi-core processor of claim 3 , wherein the target service level is to be satisfied by the power management circuitry utilizing different combinations of processing cores of the plurality of processing cores operating at different base clock frequency values.

5. The multi-core processor of claim 1 , wherein the default per-core base clock frequency values and the target per-core base clock frequency values are clock speeds at which the multi-core processor is to perform at a pre-determined level of workload within a thermal design power (TDP) limit of the multi-core processor.

6. The multi-core processor of claim 1 , wherein the power management circuitry is to expose the target per-core base clock frequency values on a hardware interface.

7. The multi-core processor of claim 6 , wherein the power management circuitry is to receive the target per-core base clock frequency values from at least one of a controller executing a basic input/output system (BIOS) instruction or from a system software application executing on the multi-core processor.

8. The multi-core processor of claim 7 , wherein the multi-core processor is to execute the system software application to retrieve the target per-core base clock frequency values via the hardware interface.

9. The multi-core processor of claim 1 , wherein the plurality of control registers include model specific registers (MSRs), an MSR associated with each of the plurality of processing cores.

10. The multi-core processor of claim 1 , wherein the power management circuitry is to adjust one or more workloads on the multi-core processor to ensure that generated thermal energy does not violate a thermal design power (TDP) associated with the multi-core processor.

11. The multi-core processor of claim 10 , wherein the power management circuitry is to adjust the one or more workloads by offloading a task to another processor or reducing the target per-core clock frequency values.

12. The multi-core processor of claim 1 , wherein at least one of the plurality of processing cores is to be run at a first per-core base clock frequency and at least one other of the plurality of processing cores is to be run at a second per-core base clock frequency.

13. The multi-core processor of claim 1 , further comprising a register to store a bit map, where each bit of the bit map stores an activity status for a corresponding processing core.

14. The multi-core processor of claim 1 , wherein the power management circuitry is to shut down one or more inactive processing cores of the plurality of processing cores and divert resulting spare power to active processing cores of the plurality of processing cores, including the corresponding processing cores of the plurality of processing cores running at the target per-core base clock frequency values.

15. The multi-core processor of claim 1 , wherein receiving the target per-core base clock frequency values and exposing the target per-core base clock frequency values to software comprises executing commands of an interface exposed by the multi-core processor.

16. A system, comprising:
a system memory to store instructions and data;
a memory controller coupled to the system memory; and
a multi-core processor coupled to the memory controller, the multi-core processor comprising:
a plurality of processing cores;
a plurality of control registers corresponding to the plurality of processing cores,
wherein each control register of the plurality of control registers is associated with a different processing core of the plurality of processing cores, the plurality of control registers to store per-core base clock frequency values corresponding to the plurality of processing cores;

the per-core base clock frequency values initially comprising default per-core base clock frequency values determined by a manufacturer of the multi-core processor; and
power management circuitry to execute firmware to control clock frequencies of the plurality of processing cores based, at least in part, on the per-core base clock frequency values;
the power management circuitry to:
receive target per-core base clock frequency values, at least some of the target per-core base clock frequency values different from corresponding default per-core base clock frequency values;
store the target per-core base clock frequency values in corresponding control registers of the plurality of control registers to cause a corresponding processing core of the plurality of processing cores to operate according to the target per-core base clock frequency values; and
expose the target per-core base clock frequency values to software.

17. The system of claim 16 , further comprising:
a graphics processor coupled to the memory controller;
one or more storage devices coupled to the memory controller; and
a plurality of input/output (IO) interfaces to couple one or more IO devices to the memory controller.

18. The system of claim 17 , wherein the target per-core base clock frequency values are determined based, at least in part, on a target service level.

19. The system of claim 18 , wherein the target service level is to indicate one or more of: a maximum power to be consumed by all or a subset of the plurality of processing cores, a thermal design power (TDP) value, and exclusivity to use one or more particular processing cores of the plurality of processing cores.

Assignees

• Intel Corp

Inventors

• Srinivasan Vasudevan
• Sistla Krishnakanth V
• Gough Corey D
• Steiner Ian M
• Gupta Nikhil
• Garg Vivek
• Varma Ankush
• Vora Sujal A
• Lerner David P
• Sullivan Joseph M
• Gurumoorthy Nagasubramanian
• Bowhill William J
• Ramamurthy Venkatesh
• Macnamara Chris
• Browne John J
• Das Ripan

Classifications

• G06F9/4893

  taking into account power or heat criteria (power management in computers in general G06F1/3203; thermal management in computers in general G06F1/206) · CPC title

• Y02D10/00

  Energy efficient computing, e.g. low power processors, power management or thermal management · CPC title

• G06F1/324

  by lowering clock frequency · CPC title

• G06F2009/45591

  Monitoring or debugging support · CPC title

• G06F9/45558

  Hypervisor-specific management and integration aspects · CPC title