Method, apparatus, and system for energy efficiency and energy conservation including configurable maximum processor current

Patent metadata

Field	Value
Publication number	US-9052901-B2
Application number	US-201113326105-A
Country	US
Kind code	B2
Filing date	Dec 14, 2011
Priority date	Dec 14, 2011
Publication date	Jun 9, 2015
Grant date	Jun 9, 2015

Abstract

An apparatus, method and system is described herein for providing multiple maximum current configuration options including corresponding turbo frequencies for a processing device. Available options for a processor are determined by initialization code. And based on platform electrical capabilities, an optimal one of the multiple current configuration options is selected. Moreover, during runtime another current configuration is dynamically selected based on current configuration considerations to provide high flexibility and best possible performance per part and computing platform.

First claim

What is claimed is:

1. A processor comprising:
a plurality of processing elements;
storage to hold a representation of a plurality of maximum current configurations for the processor, each of the maximum current configurations to be associated with a plurality of maximum turbo frequencies to be stored in the storage; and
a turbo module adapted to dynamically select a maximum current configuration of the plurality of maximum current configurations based on a power event, to determine a number of the plurality of processing elements that are active and, based on the number of the plurality of processing elements that are active, to determine a maximum turbo frequency of the plurality of maximum turbo frequencies associated with the selected maximum current configuration.

2. The processor of claim 1 , wherein the storage includes a non-volatile memory to hold a table including a plurality of maximum current values, each of the maximum current values associated with the plurality of maximum turbo frequencies.

3. The processor of claim 1 , wherein the storage includes one or more registers to hold a plurality of maximum current values associated with the plurality of maximum turbo frequencies.

4. The processor of claim 1 , wherein the power event includes removal of a power supply, and wherein the turbo module to dynamically select a maximum current configuration of the plurality of maximum current configurations that includes a smaller maximum current value than a previous maximum current value in response to the removal of the power supply.

5. The processor of claim 1 , wherein each of the maximum current configurations to be associated with a maximum turbo frequency for each integer number of the plurality of processing elements that are active.

6. The processor of claim 1 , wherein each of the maximum current configurations is to further be associated with a corresponding power event and a platform electrical metric.

7. A processor comprising:
one or more registers adapted to hold a representation of a first maximum current configuration to correspond with a first set of maximum frequencies for the processor, the one or more registers further adapted to hold a representation of the first set of maximum frequencies; and
a control module adapted to update, during runtime of the processor, the one or more registers with a representation of a second maximum current configuration of a plurality of possible maximum current configurations, the second maximum current configuration to correspond with a second set of maximum frequencies, the control module to further update the one more registers with the second set of maximum frequencies and to thereafter determine a number of a plurality of processing elements of the processor that are active and, based on the number of the plurality of processing elements that are active, determine a maximum frequency of the second set of maximum frequencies at which the processor is to operate.

8. The processor of claim 7 , wherein the one or more registers comprises one or more Model Specific Registers (MSRs).

9. The processor of claim 7 , wherein the one or more registers being adapted to hold a first maximum current value corresponding to a first set of maximum frequencies including a maximum frequency for each combination of a number of processing elements that are active in the processor.

10. The processor of claim 9 , wherein the control module being adapted to update, during runtime, the first maximum current value corresponding to the first set of maximum frequencies to a second maximum current value corresponding to the second set of maximum frequencies.

11. The processor of claim 9 , wherein the control module comprises:
Basic Input/Output Software (BIOS) adapted to expose a plurality of maximum current configurations including the first and the second maximum current configurations to the processor and to write the second maximum current configuration to the one or more registers.

12. The processor of claim 9 , wherein the control module is adapted to update the one or more registers with the representation of the second maximum current configuration in response to a power event, the power event being selected from a group consisting of plug in of a power supply, removal of a power supply, receipt of a request for more power, determination that an additional processing element is active, determination that an additional processing element is inactive, and the processor transition between power states.

13. A method comprising:
providing a set of maximum current values and corresponding turbo frequencies for a processor, wherein the set includes more than one maximum current value and each of the corresponding turbo frequencies is associated with a number of active cores of the processor; and
selecting a maximum current value and a corresponding turbo frequency of the set of maximum current values and corresponding turbo frequencies based on a maximum current configuration consideration and the number of active cores of the processor.

14. The method of claim 13 , wherein the maximum current configuration consideration includes a runtime power event, the runtime power event being selected from a group consisting of removal of a power supply, addition of a power supply, a thermal power density indicator, a workload indicator, an electrical capability indicator, and a power limit, and wherein selecting the maximum current value and the corresponding turbo frequency is performed during runtime of the processor.

15. The method of claim 13 , wherein the maximum current configuration consideration includes an electrical capability metric of a platform to include the processor.

16. The method of claim 15 , wherein providing a set of maximum current values and corresponding turbo frequencies for a processor comprises holding a table of the set of maximum current values and corresponding turbo frequencies for the processor in Basic Input/Output Software (BIOS) firmware.

17. The method of claim 16 , wherein holding a table of the set of maximum current values and corresponding turbo frequencies for the processor in Basic Input/Output Software (BIOS) firmware is in response to BIOS firmware interpreting fuses defining the set of maximum current values.

18. The method of claim 17 , wherein selecting the maximum current value and the corresponding turbo frequency of the set of maximum current values and corresponding turbo frequencies based on the electrical capability metric includes receiving information with the BIOS firmware indicating the electrical capability metric and selecting the maximum current value and the corresponding turbo frequency from the table with the BIOS firmware according to predefined policy in the BIOS firmware with respect to the electrical capability metric.

19. The method of claim 18 , wherein the electrical capability metric includes a number of phases of a voltage regulator to be associated with the processor.

Assignees

• Shah Ketan R
• Distefano Eric
• Gunther Stephen H
• Shrall Jeremy J
• Intel Corp

Inventors

• Shah Ketan R
• Distefano Eric
• Gunther Stephen H
• Shrall Jeremy J

Classifications

• G06F1/324

  by lowering clock frequency · CPC title

• G06F1/3243 Primary

  Power saving in microcontroller unit · CPC title

• G06F9/455

  Emulation; Interpretation; Software simulation, e.g. virtualisation or emulation of application or operating system execution engines · CPC title

• G06F1/3206

  Monitoring of events, devices or parameters that trigger a change in power modality · CPC title

• G06F9/4411

  Configuring for operating with peripheral devices; Loading of device drivers · CPC title