Electroless plating process

Patent metadata

Field	Value
Publication number	US-12416093-B2
Application number	US-202117482513-A
Country	US
Kind code	B2
Filing date	Sep 23, 2021
Priority date	Sep 23, 2021
Publication date	Sep 16, 2025
Grant date	Sep 16, 2025

Abstract

The present disclosure is directed to an electroless plating process using a panel basket for holding semiconductor panels comprising a plurality of metal pads and shielding the metal pads from contaminants and over-etching and under-etching caused by the contaminants.

First claim

The invention claimed is:

1. An electroless plating process comprising:
providing a panel basket;
providing semiconductor panels comprising a plurality of metal pads;
providing a pretreatment etching for the semiconductor panels comprising:
placing the semiconductor panels into the panel basket made from a basket material;
shielding the metal pads on the semiconductor panel from contaminants during the pretreatment etching to prevent over-etching and under-etching of the metal pads on the semiconductor panels; and

performing electroless plating process steps with the semiconductor panels;
wherein the panel basket is configured with two panel end plates made of the basket material and a plurality of opposing slots for carrying the semiconductor panels in and out of baths during the electroless plating process;
wherein the semiconductor panels are positioned proximal to each of the panel end plates; and
wherein the shielding the metal pads comprises providing a distance between the contaminants and the metal pads by positioning an insulating insert between the semiconductor panels and the panel end plates.

2. The electroless plating process of claim 1 , wherein the basket material is stainless steel.

3. The electroless plating process of claim 1 , wherein the insulating insert is a free-standing sheet positioned at the opposing slots.

4. The electroless plating process of claim 1 , wherein the insulating insert comprises a fluorinated polymer.

5. The electroless plating process of claim 3 , wherein the fluorinated polymer comprises polyvinylidene fluoride.

6. The electroless plating process of claim 1 , wherein the insulating insert comprises a thickness of about 10 micrometers or thicker.

7. The electroless plating process of claim 1 , wherein positioning the insulating inserts comprises direct contact of each of the insulating inserts with each of the panel end plates.

8. The electroless plating process of claim 7 , wherein the direct contact comprises the insulating insert being affixed to the panel end plate by fixation means.

9. The electroless plating process of claim 8 , wherein the insulating insert comprises a thickness of about 0.4 millimeters or thicker.

10. The electroless plating process of claim 7 , wherein the direct contact comprises the insulating insert being coated on the panel end plate.

11. The electroless plating process of claim 10 , wherein the insulating insert comprises a thickness of about 10 micrometers to about 200 micrometers.

12. The electroless plating process of claim 1 , wherein the shielding the metal pads further comprises cleaning the panel basket with nitric acid.

13. The electroless plating process of claim 12 , wherein the cleaning the panel basket with nitric acid is carried out before the semiconductor panels are placed in the panel basket.

Assignees

• Intel Corp

Inventors

• Nair Chandrasekharan
• Grujicic Darko
• Shanmugam Rengarajan
• Raman Srinivasan
• Dittler Roy
• Sowa Daniel
• Baresel Ii Robert
• Wall Marcel
• Manepalli Rahul

Classifications

• H10P72/0476 Primary

  comprising at least one plating chamber · CPC title

• C23C18/163

  Supporting devices for articles to be coated · CPC title

• C23C18/1642

  semiconductor (semiconductor H10P14/48) · CPC title

• C25D17/12

  Shape or form (C25D17/14 takes precedence) · CPC title

• C25D17/008

  Current shielding devices · CPC title