Microelectronic assemblies including interconnects with different solder materials

Patent metadata

Field	Value
Publication number	US-12412868-B2
Application number	US-202117558457-A
Country	US
Kind code	B2
Filing date	Dec 21, 2021
Priority date	Dec 21, 2021
Publication date	Sep 9, 2025
Grant date	Sep 9, 2025

Abstract

Microelectronic assemblies, related devices and methods, are disclosed herein. In some embodiments, a microelectronic assembly may include a first die, having a first surface and an opposing second surface, in a first layer; a redistribution layer (RDL) on the first layer, wherein the RDL includes conductive vias having a greater width towards a first surface of the RDL and a smaller width towards an opposing second surface of the RDL; wherein the first surface of the RDL is electrically coupled to the second surface of the first die by first solder interconnects having a first solder; and a second die in a second layer on the RDL, wherein the second die is electrically coupled to the RDL by second solder interconnects having a second solder, wherein the second solder is different than the first solder.

First claim

The invention claimed is:

1. A microelectronic assembly, comprising:
a first die, having a first surface and an opposing second surface, in a first layer;
a redistribution layer (RDL) on the first layer, wherein the RDL includes conductive vias having a greater width towards a first surface of the RDL and a smaller width towards an opposing second surface of the RDL; wherein the first surface of the RDL is electrically coupled to the second surface of the first die by first solder interconnects having a first solder; and
a second die in a second layer on the RDL, wherein the second die is electrically coupled to the RDL by second solder interconnects having a second solder, wherein the second solder is different than the first solder.

2. The microelectronic assembly of claim 1 , wherein the second solder includes a higher-temperature solder.

3. The microelectronic assembly of claim 1 , wherein second solder includes tin and copper; tin and gold; tin and silver; or tin, silver, and copper.

4. The microelectronic assembly of claim 1 , wherein the first solder includes a no remelt solder, a lower-temperature solder, or a conventional solder.

5. The microelectronic assembly of claim 4 , wherein the first solder interconnects include the lower-temperature solder or the conventional solder, and the microelectronic assembly further comprising:
an underfill material surrounding the first solder interconnects.

6. The microelectronic assembly of claim 1 , wherein the first solder interconnects include tin and bismuth; tin, silver, and bismuth; indium; indium and tin; or gallium.

7. The microelectronic assembly of claim 1 , wherein a pitch of the first solder interconnects is between 1 and 100 microns.

8. The microelectronic assembly of claim 1 , wherein a pitch of the second solder interconnects is between 50 and 150 microns.

9. The microelectronic assembly of claim 1 , wherein the first die is electrically coupled to the second die by the first solder interconnects, conductive pathways in the RDL, and the second solder interconnects.

10. The microelectronic assembly of claim 1 , further comprising:
a package substrate electrically coupled to the first surface of the first die by third solder interconnects having a third solder, wherein the third solder is different than the second solder.

11. The microelectronic assembly of claim 10 , wherein the third solder includes a no remelt solder, a lower-temperature solder, or a conventional solder.

12. A microelectronic assembly, comprising:
a first die, having a first surface with first conductive contacts and an opposing second surface with second conductive contacts, in a first layer;
a redistribution layer (RDL), having a first surface with third conductive contacts and an opposing second surface with fourth conductive contacts, on the first layer, wherein the third conductive contacts on the RDL are electrically coupled to the second conductive contacts on the first die by first solder interconnects, and wherein the first solder interconnects include a no remelt solder, a lower-temperature solder, or a conventional solder; and
a second die, having a surface with fifth conductive contacts, in a second layer on the second surface of the RDL, wherein the fifth conductive contacts on the second die are electrically coupled to the fourth conductive contacts on the RDL by second solder interconnects, wherein the second solder interconnects include a higher-temperature solder.

13. The microelectronic assembly of claim 12 , wherein the first die is electrically coupled to the second die by the first solder interconnects, conductive pathways in the RDL, and the second solder interconnects.

14. The microelectronic assembly of claim 12 , wherein the RDL further includes conductive vias having a greater width towards the first surface of the RDL and a smaller width towards the second surface of the RDL.

15. The microelectronic assembly of claim 12 , wherein the second solder interconnects include tin and copper; tin and gold; tin and silver; or tin, silver, and copper.

16. The microelectronic assembly of claim 12 , wherein the first solder interconnects include tin and bismuth; tin, silver, and bismuth; indium; indium and tin; or gallium.

17. The microelectronic assembly of claim 12 , wherein the first solder interconnects include the lower-temperature solder or the conventional solder, and the microelectronic assembly further comprising:
an underfill material surrounding the first solder interconnects.

18. A method of manufacturing a microelectronic assembly, comprising:
patterning a higher-temperature solder on a first carrier and encapsulating the higher-temperature solder with a removable protective material;
forming a redistribution layer (RDL) on the removable protective material and electrically coupling the RDL to the higher-temperature solder;
depositing a no remelt solder, a lower-temperature solder, or a conventional solder on conductive contacts on a top surface of the RDL;
attaching a first die to the no remelt solder, the lower-temperature solder, or the conventional solder on the conductive contacts on the top surface of the RDL and forming first solder interconnects;
forming a conductive pillar on one or more of the conductive contacts on the top surface of the RDL;
encapsulating a first die and the conductive pillar with an insulating material and planarizing;
depositing die-to-package substrate (DTPS) solder on conductive contacts on a top surface of the insulating material, encapsulating with a sacrificial material, and attaching a second carrier to a top surface of the sacrificial material, wherein the DTPS solder includes the no remelt solder, the lower-temperature solder, or the conventional solder;
inverting, detaching the first carrier, and removing the removable protective material;
attaching a second die to the higher-temperature solder and forming second solder interconnects; and
detaching the second carrier and removing the sacrificial material.

19. The method of claim 18 , further comprising:
attaching a package substrate to the DTPS solder and forming third solder interconnects.

20. The method of claim 19 , wherein the third solder interconnects are formed before the second solder interconnects are formed.

Assignees

• Intel Corp

Inventors

• Ecton Jeremy
• Gamba Jason M
• Marin Brandon C
• Pietambaram Srinivas V
• Sun Xiaoxuan
• Karhade Omkar G
• Brun Xavier Francois
• Li Yonggang
• Nad Suddhasattwa
• Shan Bohan
• Chen Haobo
• Duan Gang

Classifications

• H10W90/724

  between a chip and a stacked insulating package substrate, interposer or RDL · CPC title

• H10W74/15

  on active surfaces of flip-chip devices, e.g. underfills · CPC title

• H10W72/252

  comprising solid metals or solid metalloids, e.g. PbSn, Ag or Cu · CPC title

• H10W72/248

  Top-view layouts, e.g. mirror arrays · CPC title

• H10W70/685

  comprising multiple insulating layers · CPC title