Semiconductor packages and methods of manufacturing the same

Patent metadata

Field	Value
Publication number	US-12412845-B2
Application number	US-202318095513-A
Country	US
Kind code	B2
Filing date	Jan 10, 2023
Priority date	Jan 31, 2019
Publication date	Sep 9, 2025
Grant date	Sep 9, 2025

Abstract

A semiconductor package includes a substrate, a preformed feeding element, a preformed shielding element, and an encapsulant. The preformed feeding element is disposed on the substrate and the preformed feeding element is disposed on the substrate and adjacent to the preformed feeding element. The encapsulant encapsulates the preformed feeding element and the preformed shielding element.

First claim

What is claimed is:

1. A semiconductor package, comprising:
a substrate;
an electronic component disposed over the substrate;
a radio frequency (RF) structure disposed over the substrate;
a first encapsulant disposed over the substrate and encapsulating the RF structure; and
a second encapsulant disposed over the substrate and in contact with the first encapsulant, wherein an interface is between the first encapsulant and the second encapsulant, wherein a top surface of the first encapsulant is parallel to a top surface of the second encapsulant, and wherein the RF structure comprises a feeding element and a plurality of shielding elements surrounding the feeding element.

2. The semiconductor package of claim 1 , wherein a lateral surface of the RF structure is completely covered by the first encapsulant.

3. The semiconductor package of claim 1 , wherein a first distance between a first shielding element of the plurality of shielding elements and a first lateral surface of the first encapsulant is less than a second distance between the feeding element and a second lateral surface of the first encapsulant opposite to the first lateral surface.

4. The semiconductor package of claim 1 , wherein the plurality of shielding elements are in a round-like arrangement in a top view.

5. The semiconductor package of claim 1 , wherein the plurality of shielding elements are in a square-like arrangement in a top view.

6. A semiconductor package, comprising:
a substrate;
an electronic component disposed over the substrate;
a feeding element disposed over the substrate;
a first shielding element disposed over the substrate and adjacent to the feeding element;
an encapsulant encapsulating the feeding element and exposing a top surface of the feeding element; and
a shielding layer over the encapsulant, wherein a projection of the first shielding element non-overlaps the shielding layer vertically,
wherein the first shielding element and the feeding element are between an edge of the substrate and the electronic component, wherein the first shielding element is closer to the edge of the substrate than the feeding element is.

7. The semiconductor package of claim 6 , wherein the first shielding element is a hollow square, and wherein the feeding element is located within the first shielding element in a top view.

8. A semiconductor package, comprising:
a substrate;
an electronic component disposed over the substrate;
a feeding element disposed over the substrate;
a first shielding element disposed over the substrate and adjacent to the feeding element;
an encapsulant encapsulating the feeding element and exposing a top surface of the feeding element;
a shielding layer over the encapsulant, wherein a projection of the first shielding element non-overlaps the shielding layer vertically;
a second shielding element adjacent to the feeding element and opposite to the first shielding element with respect to the feeding element; and
a third shielding element adjacent to the feeding element and between the first shielding element and the second shielding element.

9. The semiconductor package of claim 8 , wherein a first imaginary line defined by the feeding element and the first shielding element is perpendicular to a second imaginary line defined by the feeding element and the third shielding element in a top view.

Assignees

• Advanced Semiconductor Eng

Inventors

• Chen cheng yuan
• Li Jiming
• Chen Chun Chen
• Yu Yuanhao

Classifications

• H10W90/724

  between a chip and a stacked insulating package substrate, interposer or RDL · CPC title

• H10W44/248

  for antennas · CPC title

• H10W74/114 Primary

  by a substrate and the encapsulations · CPC title

• H10W74/016

  using moulds · CPC title

• H10W70/093

  Connecting or disconnecting other interconnections thereto or therefrom, e.g. connecting bond wires or bumps · CPC title