Semiconductor memory device

Patent metadata

Field	Value
Publication number	US-12408324-B2
Application number	US-202218081905-A
Country	US
Kind code	B2
Filing date	Dec 15, 2022
Priority date	Mar 10, 2022
Publication date	Sep 2, 2025
Grant date	Sep 2, 2025

Abstract

A semiconductor memory device includes a substrate, a conductive line extending in a first horizontal direction above the substrate, an isolation insulating layer including a channel trench extending in a second horizontal direction intersecting with the first horizontal direction and extending from an upper surface to a lower surface of the isolation insulating layer, above the conductive line, a channel structure disposed above the conductive line, a gate electrode extending in the second horizontal direction, in the channel trench, a capacitor structure above the isolation insulating layer, and a contact structure interposed between the channel structure and the capacitor structure, wherein the channel structure includes an amorphous oxide semiconductor layer disposed in the channel trench above the conductive line, and an upper crystalline oxide semiconductor layer interposed between the amorphous oxide semiconductor layer and the contact structure.

First claim

What is claimed is:

1. A semiconductor memory device comprising:
a substrate;
a conductive line extending in a first horizontal direction above the substrate;
an isolation insulating layer comprising a channel trench extending in a second horizontal direction intersecting with the first horizontal direction and extending from an upper surface to a lower surface of the isolation insulating layer, above the conductive line;
a channel structure disposed above the conductive line;
a gate electrode extending in the second horizontal direction, in the channel trench;
a capacitor structure above the isolation insulating layer; and
a contact structure between the channel structure and the capacitor structure,
wherein the channel structure comprises an amorphous oxide semiconductor layer disposed in the channel trench above the conductive line, and an upper crystalline oxide semiconductor layer between the amorphous oxide semiconductor layer and the contact structure.

2. The semiconductor memory device of claim 1 , wherein the channel structure further comprises a lower crystalline oxide semiconductor layer interposed between the conductive line and the amorphous oxide semiconductor layer.

3. The semiconductor memory device of claim 2 , wherein the isolation insulating layer is disposed above the lower crystalline oxide semiconductor layer.

4. The semiconductor memory device of claim 2 , wherein the lower crystalline oxide semiconductor layer extends in the first horizontal direction above the conductive line.

5. The semiconductor memory device of claim 4 , wherein both side surfaces of the lower crystalline oxide semiconductor layer and both side surfaces of the conductive line are aligned in a vertical direction.

6. The semiconductor memory device of claim 1 , wherein the amorphous oxide semiconductor layer has a U-shaped vertical cross-section in the first horizontal direction.

7. The semiconductor memory device of claim 6 , wherein the upper crystalline oxide semiconductor layer comprises:
a first upper crystalline oxide semiconductor layer disposed above a first upper surface of the amorphous oxide semiconductor layer; and
a second upper crystalline oxide semiconductor layer disposed above a second upper surface of the amorphous oxide semiconductor layer and spaced apart from the first upper crystalline oxide semiconductor layer, and
wherein the amorphous oxide semiconductor layer and the first and second upper crystalline oxide semiconductor layers have the U-shaped vertical cross-section in the first horizontal direction.

8. The semiconductor memory device of claim 6 , further comprising:
a gate dielectric layer interposed between the channel structure and the gate electrode.

9. The semiconductor memory device of claim 8 , wherein the gate dielectric layer comprises:
first and second gate dielectric layers each having an L-shaped vertical cross-section along an inner surface of the channel structure, facing each other, and spaced apart from each other.

10. The semiconductor memory device of claim 1 , wherein the gate electrode comprises a first gate electrode and a second gate electrode spaced apart from each other in the first horizontal direction to face each other in the channel trench and extending in the second horizontal direction, further comprising:
a barrier insulating layer disposed between the first gate electrode and the second gate electrode; and
a gap-fill insulating layer disposed on the barrier insulating layer and filling a region between the first gate electrode and the second gate electrode.

11. A semiconductor memory device comprising:
a substrate;
a conductive line extending in a first horizontal direction above the substrate;
an isolation insulating layer comprising a channel trench extending in a second horizontal direction intersecting with the first horizontal direction and extending from an upper surface to a lower surface of the isolation insulating layer, above the conductive line;
a channel structure disposed above the conductive line;
a gate electrode extending in the second horizontal direction, in the channel trench;
a gate dielectric layer interposed between the channel structure and the gate electrode, in the channel trench;
a capacitor structure above the isolation insulating layer; and
a contact structure interposed between the channel structure and the capacitor structure,
wherein the channel structure comprises:
a lower crystalline oxide semiconductor layer extending in the first horizontal direction above the conductive line;
an amorphous oxide semiconductor layer disposed in the channel trench above the lower crystalline oxide semiconductor layer; and
an upper crystalline oxide semiconductor layer interposed between the amorphous oxide semiconductor layer and the contact structure.

12. The semiconductor memory device of claim 11 , wherein the isolation insulating layer is disposed above the lower crystalline oxide semiconductor layer such that a lower surface of the isolation insulating layer and an upper surface of the lower crystalline oxide semiconductor layer are positioned at a same vertical level.

13. The semiconductor memory device of claim 11 , wherein:
an upper surface of the upper crystalline oxide semiconductor layer is positioned at a lower vertical level than a level of an upper surface of the gate electrode, and
the contact structure is connected to the upper surface of the upper crystalline oxide semiconductor layer.

14. The semiconductor memory device of claim 11 , wherein:
the amorphous oxide semiconductor layer has a U-shaped vertical cross-section in the first horizontal direction, and
the gate dielectric layer comprises first and second gate dielectric layers each having an L-shaped vertical cross-section along an inner surface of the channel structure, facing each other, and spaced apart from each other.

15. The semiconductor memory device of claim 14 , wherein:
the gate electrode comprises a first gate electrode and a second gate electrode spaced apart from each other in the first horizontal direction to face each other in the channel trench and extending in the second horizontal direction,
the first gate dielectric layer is interposed between the channel structure and the first gate electrode, and
the second gate dielectric layer is interposed between the channel structure and the second gate electrode.

16. The semiconductor memory device of claim 14 , wherein the upper crystalline oxide semiconductor layer comprises:
a first upper crystalline oxide semiconductor layer disposed above a first upper surface of the amorphous oxide semiconductor layer; and
a second upper crystalline oxide semiconductor layer disposed above a second upper surface of the amorphous oxide semiconductor layer and spaced apart from the first upper crystalline oxide semiconductor layer, and
wherein the amorphous oxide semiconductor layer and the first and second upper crystalline oxide semiconductor layers have a U-shaped vertical cross-section in the first horizontal direction.

17. The semiconductor memory device of claim 11 , wherein the lower crystalline oxide semiconductor layer and the conductive line overlap each other in a vertical direction.

18. A semiconductor memory device comprising:
a substrate;
a conductive line extending in a first horizontal direction above the substrate;
an isolation insulating layer comprising a channel trench extending in a second horizontal direction intersecting with the first horizontal direction and extending from an upper surfa

Assignees

• Samsung Electronics Co Ltd

Inventors

• Lee Yongjin
• Kim Yongseok
• Ryu Mintae
• Ryu Huije
• Yoo Sungwon
• Lee Wonsok
• Cho Minhee

Classifications

• H10B12/482

  Bit lines · CPC title

• H10B12/34

  the transistor being at least partially in a trench in the substrate · CPC title

• H10D30/6755

  Oxide semiconductors, e.g. zinc oxide, copper aluminium oxide or cadmium stannate · CPC title

• H10D30/6728

  Vertical TFTs · CPC title

• H10B12/315 Primary

  with the capacitor higher than a bit line · CPC title