Integrated circuit device including normal cells and through via supplying backside power to frontside power gating cell

Patent metadata

Field	Value
Publication number	US-12406904-B2
Application number	US-202117562428-A
Country	US
Kind code	B2
Filing date	Dec 27, 2021
Priority date	Dec 28, 2020
Publication date	Sep 2, 2025
Grant date	Sep 2, 2025

Abstract

An integrated circuit device is provided. The integrated circuit device includes: a substrate with a first active area and a second active area spaced apart from each other in a first horizontal direction; a plurality of normal cells arranged on a first surface of the substrate; a power wiring structure arranged on a second surface of the substrate; and a power gating cell arranged on the first surface of the substrate. The power gating cell includes: a sleep control transistor arranged in the first active area; and a through via penetrating the second active area of the substrate. The power gating cell is configured to provide a virtual power voltage to the plurality of normal cells through a virtual power line based on a power voltage supplied from the power wiring structure through the through via and a power line.

First claim

What is claimed is:

1. An integrated circuit device comprising:
a substrate comprising a first active area and a second active area spaced apart from each other in a first horizontal direction;
a plurality of normal cells arranged on a first surface of the substrate;
a power wiring structure arranged on a second surface of the substrate that is opposite to the first surface;
a power gating cell arranged on the first surface of the substrate; and
a ground line extending in a second horizontal direction on the first surface of the substrate,
wherein the power gating cell comprises:
a sleep control transistor arranged in the first active area; and
a through via penetrating the second active area of the substrate, wherein the through via extends in a vertical direction from the power wiring structure to a power line, and is provided between the ground line and a virtual power line along the first horizontal direction,

wherein the power gating cell is configured to provide a virtual power voltage to the plurality of normal cells through the virtual power line based on a power voltage supplied from the power wiring structure through the through via and the power line,
wherein the virtual power line is spaced apart from the ground line in the first horizontal direction and extends in the second horizontal direction, and
wherein the power line is spaced apart from the ground line in the first horizontal direction and extends in the second horizontal direction.

2. The integrated circuit device of claim 1 , wherein the sleep control transistor comprises:
a gate electrode arranged in the first active area and configured to receive a sleep control signal;
a first impurity area arranged on a first side of the gate electrode and electrically connected to the virtual power line; and
a second impurity area arranged on a second side of the gate electrode opposite to the first side and electrically connected to the power line.

3. The integrated circuit device of claim 1 , wherein the plurality of normal cells have a first height in the first horizontal direction,
wherein the power gating cell has a second height in the first horizontal direction, and
wherein the second height is equal to the first height, or is twice, four times, or eight times the first height.

4. The integrated circuit device of claim 1 , wherein the ground line extends in the second horizontal direction across the power gating cell and at least one of the plurality of normal cells at a first vertical level,
wherein the virtual power line extends in the second horizontal direction at the first vertical level, and
wherein the power line extends in the second horizontal direction at the first vertical level.

5. The integrated circuit device of claim 1 , further comprising a deep trench isolation layer arranged on the first surface of the substrate and surrounding at least a portion of a sidewall of the through via,
wherein the deep trench isolation layer and the second active area vertically overlap.

6. The integrated circuit device of claim 1 , wherein the through via and the power line vertically overlap, and
wherein one end of the through via is in contact with a bottom surface of the power line.

7. The integrated circuit device of claim 6 , wherein the through via extends through the substrate from the first surface to the second surface.

8. The integrated circuit device of claim 1 , further comprising a buried power rail having a portion arranged in a first trench of the substrate.

9. The integrated circuit device of claim 8 , wherein one end of the through via is in contact with a bottom surface of the buried power rail.

10. An integrated circuit device comprising:
a substrate comprising a first active area and a second active area spaced apart from each other in a first horizontal direction;
a plurality of normal cells arranged on a first surface of the substrate;
a power wiring structure arranged on a second surface of the substrate that is opposite to the first surface;
a power gating cell arranged on the first surface of the substrate, and configured to provide a virtual power voltage to the plurality of normal cells through a virtual power line based on a power voltage supplied from the power wiring structure through a power line; and
a ground line extending in a second horizontal direction on the first surface of the substrate,
wherein the power gating cell comprises:
a sleep control transistor arranged in the first active area; and
a through via penetrating the second active area of the substrate, and electrically connected to the power wiring structure, wherein the through via extends in a vertical direction from the power wiring structure to the power line, and is provided between the ground line and the virtual power line along the first horizontal direction,

wherein the sleep control transistor comprises:
a gate electrode arranged in the first active area and configured to receive a sleep control signal;
a first impurity area arranged on a first side of the gate electrode; and
a second impurity area arranged on a second side of the gate electrode opposite to the first side,

wherein the virtual power line is spaced apart from the ground line in the first horizontal direction and extends in the second horizontal direction, and
wherein the power line is spaced apart from the ground line in the first horizontal direction and extends in the second horizontal direction.

11. The integrated circuit device of claim 10 , wherein the virtual power line is configured to apply the virtual power voltage to the first impurity area,
wherein the power line is configured to apply the power voltage to the second impurity area, and
wherein the power line and the through via vertically overlap.

12. The integrated circuit device of claim 11 , wherein the ground line extends in the second horizontal direction at a first vertical level on the first surface of the substrate,
wherein the virtual power line extends in the second horizontal direction at the first vertical level, and
wherein the power line extends in the second horizontal direction at the first vertical level.

13. The integrated circuit device of claim 12 , further comprising at least one dummy wiring line spaced apart from the virtual power line in the first horizontal direction at the first vertical level and extending in the second horizontal direction,
wherein the at least one dummy wiring line is electrically isolated from the through via.

14. The integrated circuit device of claim 12 , further comprising at least one dummy wiring line spaced apart from the virtual power line in the first horizontal direction at the first vertical level and extending in the second horizontal direction,
wherein a portion of the at least one dummy wiring line and the through via vertically overlap, and
wherein the portion of the at least one dummy wiring line is electrically connected to the through via.

15. The integrated circuit device of claim 12 , wherein the through via has a first width in the first horizontal direction, and
wherein the power line has a second width greater than or equal to the first width in the first horizontal direction.

16. The integrated circuit device of claim 15 , wherein the virtual power line has a third width less than or equal to the second width in the first horizontal direction.

17. The integrated circuit device of claim 16 , wherein the ground line has a fourth width equal to the third width in the first horizontal direction,
wherein each of the power line and the ground line exten

Assignees

• Samsung Electronics Co Ltd

Inventors

• Do Jungho
• Baek Sanghoon

Classifications

• H10W20/2134

  TSVs extending from the semiconductor wafer into back-end-of-line layers · CPC title

• H10W20/0234

  comprising etching via holes that stop on pads or on electrodes · CPC title

• H10W20/481

  on the rear surfaces of the wafers or substrates · CPC title

• H10W20/0242

  comprising etching via holes from the back sides of the chips, wafers or substrates · CPC title

• H10W20/427

  Power or ground buses · CPC title