Switch cell structure and method

Patent metadata

Field	Value
Publication number	US-9900005-B2
Application number	US-201615167139-A
Country	US
Kind code	B2
Filing date	May 27, 2016
Priority date	May 27, 2016
Publication date	Feb 20, 2018
Grant date	Feb 20, 2018

Abstract

A switch cell structure includes a switch cell of a first type, which includes a master switch cell and a plurality of slave switch cells. The master switch cell includes a buffer having an input and an output and a transistor having a gate coupled to the output of the buffer. The slave switch cell includes a respective signal line having an input and output and a transistor having a gate coupled to the signal line, the signal lines of the slave switch cells are coupled to one another, with the output of one coupled to the input of another of the signal lines. The output of the buffer of the master switch cell is coupled to an input of one of the signal lines of slave switch cells to drive the plurality of slave switch cells.

First claim

What is claimed is:

1. An integrated circuit structure, comprising:
a first power rail in a first metal layer;
a second power rail in the first metal layer;
a third power rail in the first metal layer;
a master switch cell disposed between the first power rail and the second power rail;
a first plurality of power straps of a first type in a second metal layer overlying and extending between the first power rail and the second power rail;
a first plurality of power straps of a second type in the second metal layer overlying and extending between the first power rail and the second power rail;
a first input strap in the second metal layer overlying the first power rail, wherein the first input strap is configured to receive a control signal different than a power signal;
a first output strap in the second metal layer overlying the second power rail;
a slave switch cell disposed between the second power rail and the third power rail;
a second plurality of power straps of the first type in the second metal layer overlying and extending between the second power rail and the third power rail;
a second plurality of power straps of the second type in the second metal layer overlying and extending between the second power rail and the third power rail; and
a first feed-through strap in the second metal layer overlying and extending between the second power rail and the third power rail, wherein the first feed-through strap passes through the slave switch cell and is configured to receive the control signal from the first output strap,
wherein the master switch cell drives the slave switch cell.

2. The structure of claim 1 , wherein at least one of the first plurality of power straps of the first type is conductively connected to an adjacent one of the second plurality of power straps of the first type.

3. The structure of claim 1 , wherein at least one of the first plurality of power straps of the first type is not conductively connected to an adjacent one of the second plurality of power straps of the first type.

4. The structure of claim 1 , wherein the first output strap and the first feed-through strap are conductively connected.

5. The structure of claim 1 , wherein the first output strap and the first feed-through strap are not conductively connected.

6. The structure of claim 1 , further comprising at least one ground strap overlying and extending between the first power rail and the second power rail in the first metal layer.

7. The structure of claim 1 , further comprising at least one ground strap overlying and extending between the second power rail and the third power rail in the first metal layer.

8. A method of creating an integrated circuit structure having a power network and switch cells, comprising:
forming a first power rail, a second power rail and a third power rail in a first metal layer;
forming a first plurality of power straps of a first type in a second metal layer overlying and extending between the first power rail and the second power rail;
forming a first input strap overlying the first power rail wherein the first input strap is configured to receive a control signal different than a power signal;
forming a first output strap overlying the second power rail;
disposing a master switch cell between the first power rail and the second power rail;
forming a second plurality of power straps of a second type in a second layer overlying and extending between the second power rail and the third power rail in the first metal layer; and
disposing a slave switch cell between the second power rail and the third power rail, the slave switch cell comprising a first feed-through strap that passes through the slave switch cell, the first feed-through strap configured to receive the control signal.

9. The method of claim 8 , further comprising:
forming the first feed-through strap in the second layer overlying and extending between the second power rail and the third power rail in the first metal layer.

10. The method of claim 8 , wherein at least one of the first plurality of power straps of the first type are conductively connected to an adjacent one of a second plurality of power straps of the first type.

11. The method of claim 8 , wherein the master switch cell comprises a buffer having an input and an output, and a transistor having a gate coupled to the output of the buffer, wherein the buffer of the master switch cell drives the slave switch cell.

12. An integrated circuit structure, comprising:
a first power rail in a first metal layer;
a second power rail in the first metal layer;
a third power rail in the first metal layer;
a master switch cell disposed between the first power rail and the second power rail;
a plurality of power straps in a second metal layer overlying and extending between the first power rail and the third power rail;
a first input strap in the second metal layer overlying the first power rail, wherein the first input strap is configured to receive a control signal different than a power signal;
a first output strap in the second metal layer overlying the second power rail;
a slave switch cell disposed between the second power rail and the third power rail; and
a first feed-through strap in the second metal layer overlying and extending between the second power rail and the third power rail, wherein the first feed-through strap passes through the slave switch cell and is configured to receive the control signal from the first output strap.

13. The integrated circuit structure of claim 12 , wherein the master switch cell comprises a transistor, wherein the transistor is electrically connected to the first power rail and the second power rail.

14. The integrated circuit structure of claim 13 , wherein the transistor in the master switch cell is a PMOS transistor.

15. The integrated circuit structure of claim 13 , wherein the transistor in the master switch cell is a NMOS transistor.

16. The integrated circuit structure of claim 12 , wherein the slave switch cell comprises a transistor, wherein the transistor is electrically connected to the second power rail and the third power rail.

17. The integrated circuit structure of claim 16 , wherein the transistor in the slave switch cell is a PMOS transistor.

18. The integrated circuit structure of claim 16 , wherein the transistor in the slave switch cell is a NMOS transistor.

19. The integrated circuit structure of claim 12 , wherein the master switch cell drives the slave switch cell.

20. The integrated circuit structure of claim 12 , further comprising a second master switch cell, and wherein an output of the slave switch cell is electrically connected to an input of the second master switch cell.

Assignees

• Taiwan Semiconductor Mfg Co Ltd

Inventors

• Chen Chih Liang
• Yu Chi Yeh
• Yu Ho Che

Classifications

• H03K17/6874 Primary

  in a symmetrical configuration · CPC title

• H03K19/0005 Primary

  Modifications of input or output impedance · CPC title