Metal lines with low via-to-via spacing

Patent metadata

Field	Value
Publication number	US-12400871-B2
Application number	US-202016795718-A
Country	US
Kind code	B2
Filing date	Feb 20, 2020
Priority date	Feb 20, 2020
Publication date	Aug 26, 2025
Grant date	Aug 26, 2025

Abstract

A method is presented for employing double-patterning to reduce via-to-via spacing. The method includes forming a mandrel layer over a substrate, forming sacrificial hardmask layers over the mandrel layer defining a litho stack, creating a pattern in the litho stack, the pattern having a narrow section connecting two wider sections to define a substantially hour-glass shape, depositing a spacer assuming a shape of the pattern, and etching the litho stack to expose the mandrel layer and metal lines, wherein the metals lines define sharp distal ends reducing a distance between the metal lines.

First claim

The invention claimed is:

1. A method for forming a semiconductor structure, the method comprising:
forming a barrier layer on a substrate;
forming a cap layer on the barrier layer;
forming a mandrel layer on the cap layer;
forming sacrificial hardmask layers over the mandrel layer defining a litho stack;
creating a pattern in the litho stack having a narrow section connecting two wider sections in an hour glass geometry;
depositing a spacer assuming a shape of the hour glass pattern; and
etching the litho stack to expose the mandrel layer and areas of the cap layer, wherein separate exposed areas of the barrier layer include respective pointed distal tips aligned with each other such that a space is defined directly between the pointed distal tips.

2. The method of claim 1 , wherein the spacer is deposited using ALD such that sides of the spacer merge.

3. The method of claim 2 , wherein the spacer establishes a distance between the pointed distal tips.

4. The method of claim 1 , wherein a tip-to-tip distance between the pointed distal tips is 39.4 nanometers (nm).

5. The method of claim 1 , wherein sidewalls of each of the exposed areas of the barrier layer converge to form a single respective point at the distal end of each exposed area.

6. The method of claim 1 , wherein the barrier layer is formed from titanium nitride.

7. The method of claim 1 , wherein forming the hardmask layers includes forming a first hardmask layer on the mandrel layer, forming a second hardmask layer on the first hardmask layer, and forming a third hardmask layer on the second hardmask layer.

8. The method of claim 7 , wherein each of the first hardmask layer, the second hardmask layer, and the third hardmask layer is formed from a different material.

9. The method of claim 7 , wherein creating a pattern in the litho stack includes selectively forming the pattern in only the third hardmask layer, before depositing the spacer.

10. The method of claim 9 , wherein etching the litho stack includes etching into the first hardmask layer, the second hardmask layer, and the mandrel layer using the spacer as a mask, leaving remaining portions of the first hardmask layer and the second hardmask layer on remaining portions of the mandrel layer.

11. The method of claim 9 , further comprising stripping the remaining portions of the first hardmask layer and the second hardmask layer and stripping portions of the cap layer to expose the barrier layer.

12. The method of claim 1 , wherein the cap layer is an insulating material containing nitrogen.

13. A method for forming a semiconductor structure, the method comprising:
forming a barrier layer;
forming a cap layer on the barrier layer;
creating a pattern in a litho stack formed over the barrier layer, the pattern having a narrow section connecting two wider sections in an hour glass geometry;
depositing a spacer assuming a shape of the pattern; and
etching the litho stack to expose separate areas of the cap layer including respective pointed distal tips aligned with each other such that a space is defined directly between the pointed distal tips.

14. The method of claim 13 , wherein the spacer is deposited using ALD such that sides of the spacer merge.

15. The method of claim 14 , wherein the spacer enables isolation between the pointed distal tips.

16. The method of claim 15 , wherein a tip-to-tip distance between the pointed distal tips is 39.4 nanometers (nm).

Assignees

• IBM

Inventors

• Dechene Daniel James
• Ghosh Somnath
• Chen Hsueh-Chung
• Radens Carl
• Clevenger Lawrence A

Classifications

• H10P76/4085 Primary

  characterised by the processes involved to create the masks · CPC title

• H10W20/089

  using processes for implementing desired shapes or dispositions of the openings, e.g. double patterning · CPC title

• H10P50/73 Primary

  using masks for insulating materials · CPC title

• H01L21/76816

  Electricity · mapped topic

• H01L21/0337

  Electricity · mapped topic