Method for etching for semiconductor fabrication

US12400863B2 · US · B2

Patent metadata
FieldValue
Publication numberUS-12400863-B2
Application numberUS-202217704372-A
CountryUS
Kind codeB2
Filing dateMar 25, 2022
Priority dateMar 25, 2022
Publication dateAug 26, 2025
Grant dateAug 26, 2025

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  1. Title

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  2. Abstract

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  3. Assignees and inventors

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  4. Key dates

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  5. First independent claim

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  6. CPC / IPC classifications

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  7. Citations and related patents

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Abstract

Official abstract text for this publication.

A method of processing a substrate includes patterning a mask over a dielectric layer and etching openings in the dielectric layer. The dielectric layer is disposed over the substrate. The etching includes flowing an etchant, a polar or H-containing gas, and a phosphorus-halide gas. The method may further include forming contacts by filling the openings with a conductive material.

First claim

Opening claim text (preview).

What is claimed is: 1. A method of processing a substrate, the method comprising: patterning a mask over a dielectric layer, the dielectric layer disposed over the substrate; etching openings in the dielectric layer, the etching comprising: flowing an etchant, a polar or H-containing gas, and a phosphorus-halide gas; and forming a catalyst comprising a phosphorus-containing acid; and forming contacts by filling the openings with a conductive material. 2. The method of claim 1 , wherein the etchant is HF or HCl. 3. The method of claim 1 , wherein the polar or H-containing gas comprises water vapor (H 2 O), hydrogen peroxide (H 2 O 2 ), hydrogen (H 2 ), a mixture of hydrogen (H 2 ) and oxygen (O 2 ), or hydrogen bromide (HBr). 4. The method of claim 1 , wherein the phosphorus-halide gas comprises phosphorus trifluoride (PF 3 ), phosphorus trichloride (PCl 3 ), phosphoryl fluoride (POF 3 ), or phosphoryl chloride (POCl 3 ). 5. The method of claim 1 , wherein the dielectric layer comprises silicon oxide or silicon nitride. 6. The method of claim 5 , wherein the dielectric layer comprises an O/N/O/N stack. 7. The method of claim 1 , wherein the etching anisotropically etches the openings in an anisotropic etch process. 8. The method of claim 7 , wherein the anisotropic etch process is performed as a plasma process in a plasma processing system. 9. The method of claim 1 , wherein the contacts have respective aspect ratios greater than 50:1. 10. A method of processing a substrate, the method comprising: performing a cyclic etching process, wherein each cycle of the cyclic etching process comprises: flowing an etchant over a dielectric layer on the substrate, the substrate being in a process chamber; forming a catalyst in the process chamber by simultaneously flowing a polar or H-containing gas and a phosphorus-halide gas over the dielectric layer in the process chamber; and purging the catalyst from the process chamber. 11. The method of claim 10 , wherein the etchant is HF. 12. The method of claim 10 , wherein the phosphorus-halide gas is phosphorus trifluoride (PF 3 ). 13. The method of claim 10 , wherein the catalyst comprises PF 2 OH. 14. The method of claim 10 , wherein the cyclic etching process is a plasma process. 15. The method of claim 10 , wherein the cyclic etching process is anisotropic. 16. A method of processing a substrate in a process chamber, the method comprising: simultaneously flowing an etchant and a polar or H-containing gas over a dielectric layer comprising an exposed surface of the substrate; and performing a cyclic tuning process, wherein each cycle of the cyclic tuning process comprises: adjusting a temperature of the process chamber; and flowing a phosphorus-halide gas over the dielectric layer. 17. The method of claim 16 , wherein the polar or H-containing gas comprises H 2 O. 18. The method of claim 16 , wherein the phosphorus-halide gas comprises phosphorus and fluorine. 19. The method of claim 16 , wherein the dielectric layer comprises silicon oxide. 20. The method of claim 16 , further comprising forming an opening in the dielectric layer, the opening having an aspect ratio greater than 50:1.

Assignees

Inventors

Classifications

  • H10P50/242Primary

    of Group IV materials · CPC title

  • H10P50/283Primary

    by chemical means · CPC title

  • Etching · CPC title

  • Gas control, e.g. control of the gas flow · CPC title

  • Circuits specially adapted for controlling the RF discharge · CPC title

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What does patent US12400863B2 cover?
A method of processing a substrate includes patterning a mask over a dielectric layer and etching openings in the dielectric layer. The dielectric layer is disposed over the substrate. The etching includes flowing an etchant, a polar or H-containing gas, and a phosphorus-halide gas. The method may further include forming contacts by filling the openings with a conductive material.
Who is the assignee on this patent?
Tokyo Electron Ltd
What technology area does this patent fall under?
Primary CPC classification H10P50/242. Mapped technology areas include Electricity.
When was this patent published?
Publication date Tue Aug 26 2025 00:00:00 GMT+0000 (Coordinated Universal Time) (B2). Legal status and post-grant events are not shown on this page.
What related patents are in patentsdb?
We list 5 related publications on this page (citations in our corpus or others sharing the same primary CPC).