Firmware first handling of a machine check event

Patent metadata

Field	Value
Publication number	US-12399780-B2
Application number	US-202217711465-A
Country	US
Kind code	B2
Filing date	Apr 1, 2022
Priority date	Apr 1, 2022
Publication date	Aug 26, 2025
Grant date	Aug 26, 2025

Abstract

Techniques and mechanisms for supporting machine check functionality with a handler which is implemented in firmware. In an embodiment, a processor executes first firmware code to implement a machine check event (MCE) detector. The MCE detector detects a hardware error of a platform which includes the processor, and generates a call to invoke an MCE handler which the processor implements by executing second firmware code. The MCE handler is called, outside of a software context, to attempt a recovery from the hardware error. The call is performed independent of any system management interrupt being based on the detected hardware error. In another embodiment, another MCE handler of an operating system is conditionally invoked where it is determined that the attempted recovery by the first MCE handler was unsuccessful.

First claim

What is claimed is:

1. One or more non-transitory computer-readable storage media having stored thereon instructions to cause a processor to perform a method comprising:
executing first firmware code to provide a machine check event (MCE) detector, wherein the MCE detector is to:
detect a hardware error;
access first information from an architectural register of the processor, wherein the first information identifies a location of second firmware code in a memory; and
generate a call, based on both the hardware error and the first information, to invoke an MCE handler;

wherein, based on the call, the second firmware code is executed to provide the MCE handler, wherein the MCE handler performs an attempt to recover from the hardware error.

2. The one or more non-transitory computer-readable storage media of claim 1 , wherein the MCE detector is to invoke the MCE handler independent of any generation of a system management interrupt based on the hardware error.

3. The one or more non-transitory computer-readable storage media of claim 1 , wherein the MCE handler is further to generate second information which indicates whether the attempt was successful; and
wherein, after a return from the MCE handler, the MCE detector is further to determine, based on the second information, whether to invoke a second MCE handler of an operating system.

4. The one or more non-transitory computer-readable storage media of claim 1 , the method further comprising:
with a basic input output system (BIOS), loading the second firmware code to the location; and
with the BIOS, storing the first information to the architectural register of the processor.

5. The one or more non-transitory computer-readable storage media of claim 1 , wherein the MCE handler is a single threaded process.

6. The one or more non-transitory computer-readable storage media of claim 1 , wherein the MCE handler is a ring 0 process.

7. The one or more non-transitory computer-readable storage media of claim 1 , the method further comprising:
providing an interface between an operating system executed with the processor, and one of the MCE detector or the MCE handler, wherein the interface is compatible with a Unified Extensible Firmware Interface standard; and
authenticating the second firmware code with a Secure Boot feature of the interface.

8. The one or more non-transitory computer-readable storage media of claim 1 , wherein the MCE handler is to access one or more other architectural registers of the processor to identify a type of information to be included in a report of a machine check event.

9. The one or more non-transitory computer-readable storage media of claim 8 , wherein the MCE handler is to provide the report to a mailbox region of the memory.

10. A method at a processor, the method comprising:
executing first firmware code to provide a machine check event (MCE) detector, wherein the MCE detector is to:
detect a hardware error;
access first information from an architectural register of the processor, wherein the first information identifies a location of second firmware code in a memory; and
generate a call, based on both the hardware error and the first information, to invoke an MCE handler; and

based on the call, executing the second firmware code to provide the MCE handler, wherein the MCE handler performs an attempt to recover from the hardware error.

11. The method of claim 10 , wherein the MCE detector is to invoke the MCE handler independent of any generation of a system management interrupt based on the hardware error.

12. The method of claim 10 , wherein the MCE handler is further to generate second information which indicates whether the attempt was successful; and
wherein, after a return from the executing of the second firmware code, the MCE detector is further to determine, based on the second information, whether to invoke a second MCE handler of an operating system.

13. The method of claim 10 , further comprising:
with a basic input output system (BIOS), loading the second firmware code to the location; and

with the BIOS, storing the first information to the architectural register of the processor.

14. The method of claim 10 , wherein the MCE handler is a single threaded process.

15. The method of claim 10 , wherein the MCE handler is a ring 0 process.

16. One or more non-transitory computer-readable storage media having stored thereon instructions to cause a processor to perform a method comprising:
with a basic input output system (BIOS), loading first firmware code to a location in a memory; and
with the BIOS, storing first information to an architectural register of the processor, wherein the first information identifies the location, wherein the architectural register is to be accessible to a hardware error detector which is to be provided with second firmware code;

wherein an execution of the second firmware code is to provide a machine check event (MCE) detector, wherein the MCE detector is to:
detect a hardware error;
access the first information at the architectural register; and
generate a call, based on both the hardware error and the first information, to invoke an MCE handler; and

wherein, based on the call, the first firmware code is to be executed to provide the MCE handler, wherein the MCE handler is to perform an attempt to recover from the hardware error.

17. The one or more non-transitory computer-readable storage media of claim 16 , wherein the MCE detector is to invoke the MCE handler independent of any generation of a system management interrupt based on the hardware error.

18. The one or more non-transitory computer-readable storage media of claim 16 , wherein the MCE handler is further to generate second information which indicates whether the attempt was successful; and
wherein, after a return from the executing of the second firmware code, the MCE detector is further to determine, based on the second information, whether to invoke a second MCE handler of an operating system.

19. The one or more non-transitory computer-readable storage media of claim 16 , wherein the MCE handler is a single threaded process.

20. The one or more non-transitory computer-readable storage media of claim 16 , wherein the MCE handler is a ring 0 process.

Assignees

• Intel Corp

Inventors

• Jayakumar Sarathy
• Konduru Eswar
• Holm John

Classifications

• G06F11/1417

  Boot up procedures · CPC title

• G06F21/575

  Secure boot · CPC title

• G06F11/0784

  Routing of error reports, e.g. with a specific transmission path or data flow · CPC title

• G06F11/0772

  Means for error signaling, e.g. using interrupts, exception flags, dedicated error registers · CPC title

• G06F2221/033

  Test or assess software · CPC title