Apparatus and method for vectored machine check bank reporting

Patent metadata

Field	Value
Publication number	US-10824496-B2
Application number	US-201715857376-A
Country	US
Kind code	B2
Filing date	Dec 28, 2017
Priority date	Dec 28, 2017
Publication date	Nov 3, 2020
Grant date	Nov 3, 2020

Abstract

An apparatus and method for machine check bank reporting in a processor. For example, one embodiment includes a processor comprising: one or more cores to execute instructions and process data; a plurality of machine check architecture banks to store errors detected during execution of the instructions; error monitoring circuitry to detect the errors and responsively update the MCA banks; and a first error register (FERR) into which a first error vector is to be stored to identify an MCA bank containing a first error in an error sequence, the error monitoring circuitry to update the first error vector responsive to detecting the first error; and one or more next error registers (NERRs) to store one or more error vectors to one or more other MCA banks containing subsequent errors occurring after the first error.

First claim

What is claimed is:

1. A processor comprising:
one or more cores to execute instructions and process data;
a plurality of machine check architecture (MCA) banks to store errors detected during execution of the instructions;
error monitoring circuitry to detect the errors and responsively update the MCA banks;
a first error register (FERR) into which a first error vector is to be stored to identify an MCA bank containing first error data recorded responsive to a first error during an error sequence, the error monitoring circuitry to update the first error vector responsive to detecting the first error;
execution circuity to execute a machine check handler, the machine check handler to read the first error vector from the FERR to identify the MCA bank containing the first error data to be traversed ahead of any other MCA banks; and
one or more next error registers (NERRs) to store one or more error vectors to one or more other MCA banks containing subsequent error data recorded responsive to one or more errors occurring after the first error.

2. The processor of claim 1 wherein at least one of the MCA banks is a merged MCA bank to store different types of errors generated from various different functional units and/or processing stages of the processor.

3. The processor of claim 1 wherein the error monitoring circuitry comprises circuitry within one or more cores and/or circuitry outside of the one or more cores.

4. The processor of claim 1 wherein the machine check handler is to read the first error data from the first MCA bank identified by the first error vector.

5. The processor of claim 4 wherein the machine check handler is to read a first NERR to identify the existence of second error data recorded after the first error data in the error sequence.

6. The processor of claim 5 wherein the machine check handler is to read the second error data from a second MCA bank identified by the second error vector.

7. The processor of claim 6 wherein the machine check handler is to determine whether any other NERRs include one or more additional error vectors recorded in response to one or more additional errors occurring in sequence following the second error.

8. The processor of claim 7 wherein the machine check handler is to read third error data from a third MCA bank identified by a third error vector of the additional error vectors.

9. The processor of claim 8 wherein the machine check handler is to analyze data read from the MCA banks and execute a recovery action if possible and/or required.

10. A method comprising:
executing instructions and processing data;
storing errors detected during execution of the instructions in a plurality of machine check architecture (MCA) banks;
detecting the errors and responsively updating the MCA banks;
storing a first error vector in a first error register (FERR) to identify an MCA bank containing first error data in an error sequence;
updating the first error vector responsive to detecting the first error;
reading the first error vector from the FERR to identify the MCA bank containing the first error data to be traversed ahead of any other MCA banks; and
storing in one or more next error registers (NERRs) one or more additional error vectors to identify one or more other MCA banks containing additional error data recorded subsequent to the first error.

11. The method of claim 10 wherein at least one of the MCA banks is a merged MCA bank to store different types of errors generated from various different functional units and/or processing stages of a processor.

12. The method of claim 10 wherein the detection of the errors is performed by circuitry within one or more cores of a processor and/or circuitry outside of the one or more cores.

13. The method of claim 10 further comprising:
reading the first error data from the first MCA bank identified by the first error vector.

14. The method of claim 13 further comprising:
reading a first NERR to identify the existence of second error data recorded after the first error data in the error sequence.

15. The method of claim 14 furthering comprising:
reading the second error data from a second MCA bank identified by the second error vector.

16. The method of claim 15 further comprising:
determining whether any other NERRs include one or more additional error vectors recorded in response to one or more additional errors occurring in sequence following the second error.

17. The method of claim 16 further comprising:
reading third error data from a third MCA bank identified by a third error vector of the additional error vectors.

18. The method of claim 17 further comprising:
analyzing data read from the MCA banks and executing a recovery action if possible and/or required.

19. A non-transitory machine-readable medium having program code stored thereon which, when executed by a machine, causes the machine to perform the operations of:
executing instructions and processing data;
storing errors detected during execution of the instructions in a plurality of machine check architecture (MCA) banks;
detecting the errors and responsively updating the MCA banks;
storing a first error vector in a first error register (FERR) to identify an MCA bank containing first error data in an error sequence;
reading the first error vector from the FERR to identify the MCA bank containing the first error data to be traversed ahead of any other MCA banks;
updating the first error vector responsive to detecting the first error; and
storing in one or more next error registers (NERRs) one or more additional error vectors to identify one or more other MCA banks containing additional error data recorded subsequent to the first error.

20. The non-transitory machine-readable medium of claim 19 wherein at least one of the MCA banks is a merged MCA bank to store different types of errors generated from various different functional units and/or processing stages of a processor.

21. The non-transitory machine-readable medium of claim 19 wherein the detection of the errors is performed one or more cores of a processor and/or circuitry outside of the one or more cores.

22. The non-transitory machine-readable medium of claim 19 , the operations further comprising:
reading the first error data from the first MCA bank identified by the first error vector.

23. The non-transitory machine-readable medium of claim 22 , the operations further comprising:
reading a first NERR to identify the existence of second error data recorded after the first error data in the error sequence.

24. The non-transitory machine-readable medium of claim 23 , the operations further comprising:
reading the second error data from a second MCA bank identified by the second error vector.

25. The non-transitory machine-readable medium of claim 24 , the operations further comprising:
determining whether any other NERRs include one or more additional error vectors recorded in response to one or more additional errors occurring in sequence following the second error.

26. The non-transitory machine-readable medium of claim 25 , the operations further comprising:
reading third error data from a third MCA bank identified by a third error vector of the additional error vectors.

27. The non-transitory machine-readable medium of claim 26 , the operations further comprising:
analyzing data read from the MCA banks

Assignees

• Intel Corp

Inventors

• Panda Subhankar
• Porwal Gaurav
• Holm John G

Classifications

• G06F11/0751

  Error or fault detection not based on redundancy (power supply failures G06F1/30; network fault management H04L41/06) · CPC title

• G06F11/0793

  Remedial or corrective actions (recovery from an exception in an instruction pipeline G06F9/3861; by retry G06F11/1402; for recovering from a failure of a protocol instance or entity H04L69/40) · CPC title

• G06F11/0772

  Means for error signaling, e.g. using interrupts, exception flags, dedicated error registers · CPC title

• G06F11/0787 Primary

  Storage of error reports, e.g. persistent data storage, storage using memory protection · CPC title

• G06F11/0724 Primary

  in a multiprocessor or a multi-core unit (multiprocessors per se G06F15/80) · CPC title