Delayed error processing

US10929232B2 · US · B2

Patent metadata
FieldValue
Publication numberUS-10929232-B2
Application numberUS-201715610067-A
CountryUS
Kind codeB2
Filing dateMay 31, 2017
Priority dateMay 31, 2017
Publication dateFeb 23, 2021
Grant dateFeb 23, 2021

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  1. Title

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  2. Abstract

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  3. Assignees and inventors

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  4. Key dates

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  5. First independent claim

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  6. CPC / IPC classifications

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  7. Citations and related patents

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Abstract

Official abstract text for this publication.

A computing apparatus, including: a hardware platform including a processor and memory; and a system management interrupt (SMI) handler; first logic configured to provide a first container and a second container via the hardware platform; and second logic configured to: detect an uncorrectable error in the first container; responsive to the detecting, generate a degraded system state; provide a degraded state message to the SMI handler; instruct the second container to seek a recoverable state; determine that the second container has entered a recoverable state; and initiate a recovery operation.

First claim

Opening claim text (preview).

What is claimed is: 1. A computing apparatus, comprising: a hardware platform comprising a processor and memory; and a system management interrupt (SMI) handler; first logic configured to provide a first container and a second container via the hardware platform; and second logic configured to: detect an uncorrectable system-level error caused by the first container, wherein the uncorrectable system-level error affects the first container and the second container; responsive to the detecting, generate a degraded system state; provide a degraded state message to the SMI handler; instruct the second container to seek a recoverable state; determine that the second container has entered a recoverable state; and after verifying that the second container has entered the recoverable state, initiate a recovery operation. 2. The computing apparatus of claim 1 , wherein the second logic is further configured to set a timeout, and to initiate the recovery operation after expiration of the timeout. 3. The computing apparatus of claim 1 , further comprising a fabric interface, wherein the second logic is further to provide degradation notification to a controller. 4. The computing apparatus of claim 3 , wherein the second logic is further to request the controller to spawn a new instance of a service provided by the first container. 5. The computing apparatus of claim 1 , wherein the recoverable state comprises a state in which the second container can be migrated with minimal data loss. 6. The computing apparatus of claim 5 , wherein the second logic is further configured to migrate the second container. 7. The computing apparatus of claim 1 , further comprising an operating system, further configured to perform a core dump of the first container. 8. The computing apparatus of claim 7 , wherein the operating system is configured to receive machine check architecture (MCA) logging information from the processor. 9. The computing apparatus of claim 7 , wherein the second logic is further configured to notify the operating system of the degraded state of the apparatus. 10. The computing apparatus of claim 1 , wherein the second logic further comprises a configuration interface configured to receive configuration options. 11. One or more tangible, non-transitory computer-readable mediums having stored thereon instructions for providing logic to: provide a system management interrupt (SMI) handler; provide a first container and a second container; detect an uncorrectable system-level error caused by the first container, wherein the uncorrectable system-level error affects the first container and the second container; responsive to the detecting, generate a degraded system state; provide a degraded state message to the SMI handler; instruct the second container to seek a recoverable state; determine that the second container has entered a recoverable state; and after verifying that the second container has entered the recoverable state, initiate a recovery operation. 12. The one or more tangible, non-transitory computer-readable mediums of claim 11 , wherein the logic is further configured to set a timeout, and to initiate the recovery operation after expiration of the timeout. 13. The one or more tangible, non-transitory computer-readable mediums of claim 11 , wherein the logic is further to provide degradation notification to a controller via a fabric interface. 14. The one or more tangible, non-transitory computer-readable mediums of claim 13 , wherein the logic is further to request the controller to spawn a new instance of a service provided by the first container. 15. The one or more tangible, non-transitory computer-readable mediums of claim 11 , wherein the recoverable state comprises a state in which the second container can be migrated with minimal data loss. 16. The one or more tangible, non-transitory computer-readable mediums of claim 15 , wherein the logic is further configured to migrate the second container. 17. The one or more tangible, non-transitory computer-readable mediums of claim 11 , wherein the logic is further configured to provide an operating system configured to perform a core dump of the first container. 18. The one or more tangible, non-transitory computer-readable mediums of claim 17 , wherein the operating system is configured to receive machine check architecture (MCA) logging information from the logic. 19. The one or more tangible, non-transitory computer-readable mediums of claim 17 , wherein the logic is further configured to notify the operating system of the degraded state of the first container. 20. The one or more tangible, non-transitory computer-readable mediums of claim 11 , wherein the logic further comprises a configuration interface configured to receive configuration options. 21. A computer-implemented method of providing delayed error processing, comprising: providing a system management interrupt (SMI) handler; providing a first container and a second container; detecting an uncorrectable system-level error caused by the first container, wherein the uncorrectable system-level error affects the first container and the second container; responsive to the detecting, generating a degraded system state; providing a degraded state message to the SMI handler; instructing the second container to seek a recoverable state; determining that the second container has entered a recoverable state; and after verifying that the second container has entered the recoverable state, initiating a recovery operation. 22. The method of claim 21 , further comprising setting a timeout, and to initiate the recovery operation after expiration of the timeout. 23. The method of claim 21 , further comprising providing degradation notification to a controller via a fabric interface. 24. The method of claim 23 , further comprising requesting the controller to spawn a new instance of a service provided by the first container. 25. The method of claim 21 , wherein the recoverable state comprises a state in which the second container can be migrated with minimal data loss.

Assignees

Inventors

Classifications

  • in a virtual computing platform, e.g. logically partitioned systems · CPC title

  • Restarting or rejuvenating · CPC title

  • Remedial or corrective actions (recovery from an exception in an instruction pipeline G06F9/3861; by retry G06F11/1402; for recovering from a failure of a protocol instance or entity H04L69/40) · CPC title

  • by exceeding a time limit, i.e. time-out, e.g. watchdogs · CPC title

  • Virtual · CPC title

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Frequently asked questions

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What does patent US10929232B2 cover?
A computing apparatus, including: a hardware platform including a processor and memory; and a system management interrupt (SMI) handler; first logic configured to provide a first container and a second container via the hardware platform; and second logic configured to: detect an uncorrectable error in the first container; responsive to the detecting, generate a degraded system state; provide a…
Who is the assignee on this patent?
Intel Corp
What technology area does this patent fall under?
Primary CPC classification G06F11/1438. Mapped technology areas include Physics.
When was this patent published?
Publication date Tue Feb 23 2021 00:00:00 GMT+0000 (Coordinated Universal Time) (B2). Legal status and post-grant events are not shown on this page.
What related patents are in patentsdb?
We list 7 related publications on this page (citations in our corpus or others sharing the same primary CPC).